+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Member level 2
    Points: 683, Level: 5

    Join Date
    Apr 2018
    Posts
    50
    Helped
    0 / 0
    Points
    683
    Level
    5

    Adding '1' to a std_logic_vector in VHDL

    I'm having an error about adding 1 to a std_logic_vector in VHDl.

    Here's the code: It's a 74LS163 Synchronous Binary Counter code.

    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    
    
    entity AAC2M2P1 is port (                 	
       CP: 	in std_logic; 	-- clock
       SR:  in std_logic;  -- Active low, synchronous reset
       P:    in std_logic_vector(3 downto 0);  -- Parallel input
       PE:   in std_logic;  -- Parallel Enable (Load)
       CEP: in std_logic;  -- Count enable parallel input
       CET:  in std_logic; -- Count enable trickle input
       Q:   out std_logic_vector(3 downto 0);            			
        TC:  out std_logic  -- Terminal Count
    );            		
    end AAC2M2P1;
    
    architecture LS163 of AAC2M2P1 is
    signal temp: std_logic_vector(0 to 3);
    signal RCO: std_logic;
    	begin process(CP, SR, PE)
    		begin
    			if 	(SR = '1') then
    			temp <= "0000";
    			elsif (rising_edge(CP)) then
    				if (PE = '0') then
    					temp <= P;
    					if (temp = "1111") then
    					temp <= "0000";
    					RCO <= '1';
    					else 
    					temp <= temp + 1;  --ERROR
    					RCO <= '0';
    					end if;
    				end if;
    			end if;
    		end process;
    	Q <= temp;
    	TC <= RCO;
    	end LS163;
    I used 1076-2008 in ModelSim - Altera, as "temp <= temp + 1" should be synthesizable but it still got an error when simulated -- No feasible entries for inflix operator '+'.
    I tried using x"1", x"0001" and '1' but all of these didn't worked.

    Also, how should I write the code for using CEP and CET as count enables.
    Last edited by chandlerbing65nm; 23rd March 2020 at 16:59.

    •   AltAdvertisement

        
       

  2. #2
    Member level 4
    Points: 915, Level: 6

    Join Date
    Jun 2017
    Location
    near the sea
    Posts
    73
    Helped
    15 / 15
    Points
    915
    Level
    6

    Re: Adding '1' to a std_logic_vector in VHDL

    Make temp unsigned, then you can perform arithmetic on it.
    When you output it to Q, cast it as std_logic_vector


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  3. #3
    Super Moderator
    Points: 32,398, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,489
    Helped
    1758 / 1758
    Points
    32,398
    Level
    43

    Re: Adding '1' to a std_logic_vector in VHDL

    Quote Originally Posted by chandlerbing65nm View Post
    I used 1076-2008 in ModelSim - Altera, as "temp <= temp + 1" should be synthesizable but it still got an error when simulated -- No feasible entries for inflix operator '+'.
    I tried using x"1", x"0001" and '1' but all of these didn't worked.
    adding std_logic_vectors is not supported in the numeric_std library as fourtytwo suggests use unsigned which does support arithmetic operations.

    Also, how should I write the code for using CEP and CET as count enables.
    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    
    process(clk)
    begin
      if rising_edge(clk) then
        if (CEP = '1') then   -- counts when high
          CEP_enabled_counter <= CEP_enabled_counter + 1;
        end if;
      end if;
    end process;


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 38,490, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,960
    Helped
    2051 / 2051
    Points
    38,490
    Level
    47

    Re: Adding '1' to a std_logic_vector in VHDL

    Or use VHDL 2008. The numeric_std_unsigned package allows unsigned arithmatic on std_logic_vector, even allowing the perenial student compilation error - adding a std_logic to a std_logic_vector

    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    
    use ieee.numeric_std_unsigned.all;
     
    signal cnt : std_logic_vector(15 downto 0);
     
    process(clk)
    begin
      if rising_edge(clk)
        cnt <= cnt + '1';
      end if;
    end process;



  5. #5
    Member level 2
    Points: 683, Level: 5

    Join Date
    Apr 2018
    Posts
    50
    Helped
    0 / 0
    Points
    683
    Level
    5

    Re: Adding '1' to a std_logic_vector in VHDL

    I got this final code:

    Code:
    architecture LS163 of AAC2M2P1 is
    signal temp: unsigned(3 downto 0);
    signal RCO: std_logic;
    signal count_enables: std_logic;
    
    	begin
    	count_enables <= CEP and CET;
    		process(CP, SR, PE, P) begin
    			if 	(SR = '0') then
    			temp <= "0000";
    			elsif (rising_edge(CP)) then
    				if (PE = '1') then
    					temp <= unsigned(P);
    					if count_enables = '1' then
    						if (temp = "1111") then
    						RCO <= '1';
    						temp <= "0000";
    						else 
    						RCO <= '0';
    						temp <= temp + 1;
    						end if;
    					end if;
    				end if;
    			end if;
    		end process;
    	Q <= std_logic_vector(temp);
    	TC <= RCO;
    	end LS163;
    and this is the waveform from ModelSim - Altera:
    Click image for larger version. 

Name:	counter.PNG 
Views:	5 
Size:	104.8 KB 
ID:	158369

    But the auto grader scored it 5/10 (at online course), (It count up until F for a given time period though). It must be that some of the functions of 74LS163 is not used or misused. If someone could look ever what I'm missing, that will be helpful. Thanks



    •   AltAdvertisement

        
       

  6. #6
    Advanced Member level 4
    Points: 7,907, Level: 21
    Achievements:
    7 years registered

    Join Date
    Jul 2010
    Location
    Sweden
    Posts
    1,061
    Helped
    403 / 403
    Points
    7,907
    Level
    21

    Re: Adding '1' to a std_logic_vector in VHDL

    The TC output is wrong, should be '1' when the counter is "1111" and CET = '1'.
    The parallel load is wrong, should happen when PE = '0', regardless of CEP and CET.
    An unsigned signal will wrap automatically from "1111" to "0000", so you don't need code for that.


    1 members found this post helpful.

  7. #7
    Member level 2
    Points: 683, Level: 5

    Join Date
    Apr 2018
    Posts
    50
    Helped
    0 / 0
    Points
    683
    Level
    5

    Re: Adding '1' to a std_logic_vector in VHDL

    I got the right answer with 1 error in TC. Scored 9/10 but still curious what is the error in TC.

    Here's the updated code.
    Code:
    architecture LS163 of AAC2M2P1 is
    signal temp: unsigned(3 downto 0);
    signal RCO: std_logic;
    signal count_enables: std_logic;
    
    	begin
    	count_enables <= CEP and CET;
    		counter: process(CP) begin
    			if 	rising_edge(CP) then
    				if SR = '0' then
    				temp <= "0000";
    				elsif SR = '1' and PE = '0' then
    				temp <= unsigned(P);
    				elsif SR = '1' and PE = '1' and count_enables = '1' then
    				temp <= temp + 1;
    				end if;
    			end if;
    		end process counter;
    		Q <= std_logic_vector(temp);
    		
    		carry: process(P, CET) begin
    			if CET = '1' then
    				RCO <= P(0) and P(1) and P(2) and P(3);
    			else
    				RCO <= '0';
    			end if;
    		end process carry;
    		TC <= RCO;
    		
    	end LS163;
    Here's the waveform in ModelSim.
    Click image for larger version. 

Name:	counter.PNG 
Views:	3 
Size:	230.2 KB 
ID:	158382



  8. #8
    Super Moderator
    Points: 265,394, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    46,367
    Helped
    14113 / 14113
    Points
    265,394
    Level
    100

    Re: Adding '1' to a std_logic_vector in VHDL

    RCO is evaluating P input but should evaluate temp respectively Q.


    1 members found this post helpful.

--[[ ]]--