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[SOLVED] How to automate the maximum frequency estimation

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noureddine-as

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I am using Design Compiler to synthesize a set of circuits. The goal is to find for each circuit the Maximum frequency and the corresponding Area.

Normally for a single circuit I would set an initial clock frequency in the constraints, then I'd synthesize, and check if the constraints are not met, I'd decrease ...etc. So my question is, is there any automated way of doing that automatically?

I would also like to have an Area vs. Frequency graph for each circuits, so same question about the automation process? or if there is any built-in functionality that does that in DC.

I'm a beginner in HW synthesis, so any ideas or pointers to documentations or open-source projects is appreciated.

Thanks.
 

noureddine-as said:
I am using Design Compiler to synthesize a set of circuits. The goal is to find for each circuit the Maximum frequency and the corresponding Area.

Normally for a single circuit I would set an initial clock frequency in the constraints, then I'd synthesize, and check if the constraints are not met, I'd decrease ...etc. So my question is, is there any automated way of doing that automatically?

I would also like to have an Area vs. Frequency graph for each circuits, so same question about the automation process? or if there is any built-in functionality that does that in DC.

I'm a beginner in HW synthesis, so any ideas or pointers to documentations or open-source projects is appreciated.

Thanks.
Click to expand...

I have seen people do two approaches:
- start from impossible constraint (1ps clock period) and relax as you go.
- start from relaxed constraint (99999999ps clock period) and tighten as you go.

both can be scripted, albeit not easily. I have done it by exporting the timing report, parsing it in my own C++ tool, and creating a new SDC file based on that. It's not a lot of work, but it takes some playing around.

One alternative I have seen people try is to run dc with clock frequency #1, then adjust the frequency to #2, and run only the synthesis optimization again. this leads to poor results. I would recommend closing the tool altogether and starting from scratch each time you change the clock.
 

Hi,

I have seen people do two approaches:
Click to expand...
I'm not experienced in this field ... but can't the approach be done in "binary search" style to reduce processing time?

Define two frequencies first:
* a known "will work" frequency
* a known "will not work" frequency

******
Another idea: the report should show you the slowest path....with it's timing.
You may use this to calculate the max clock frequency.

Klaus
 

KlausST said:
Hi,


I'm not experienced in this field ... but can't the approach be done in "binary search" style to reduce processing time?

Define two frequencies first:
* a known "will work" frequency
* a known "will not work" frequency

******
Another idea: the report should show you the slowest path....with it's timing.
You may use this to calculate the max clock frequency.

Klaus
Click to expand...

the binary search wouldn't necessarily reduce the time. in typical binary search problems, you are interested in exploring both branches of the solution space. here is different because both branches lead to the same spot in the solution space.


and about the report, the path changes as you keep squeezing it. the tools will run different optimisation tricks depending on how close to the limits you are. the process really has to be iterative, there is no way around it to the best of my knowledge.
 

Thank you very much for these insights. Although it will still be manual for me, at least I have some tricks to speed things a little bit. Thanks all!
 

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