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Non Overlapping Clock Generator(4 outputs with same frequencies as the input clock)

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cb258

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Hello,

I want to design (using only digital logic components) a Non-Overlapping clock generator with 4 output clocks and one input clock.
I was able to design it using flip-flops but with half the frequency of the input clock(Fin). To overcome this issue, I can use a frequency multiplier (Fin*2) , but this solution will increase the complexity of the design.
Is there any other method/way to design Non-Overlapping clock generator (with output frequencies == input frequency).

Thank you.
 

For fixed frequency, analog delay elements (LC, RC, transmission line) or logic gate delays may be used. They are however prone to PVT (process, voltage, temperature) variations. For variable frequency and PVT cancellation, PLL or DLL designs are the way to go.

PLL clock generation is widely available with modern FPGA, DLL is often used in built-in dedicated interfaces , e.g. for DDR RAM.
 
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    cb258

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If all you want is "enough" switch throw time nonoverlap
then you could do it with combo logic and delay stages.
Tuning it up to match will be an exercise and from there
PVT "is what it is".
 
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Hi,

Not strictly digital logic components, but in Curing Comparator Instability with Hysteresis, the introductory paragraph mentions one use for a comparator as clock recovery, don't know if that could apply to what you want. I understood it as 1 clock in > 4 identical clocks out, but from other, much more informed, answers I think I may not understand your design goal.
 

A chaser or sequencer circuit can be built using several stages, each stage having components such as capacitor, diode, resistor, logic gate.
If you adjust everything properly, an incoming clock pulse triggers a train of one-shots.
 

Hello,

I want to design (using only digital logic components) a Non-Overlapping clock generator with 4 output clocks and one input clock.
I was able to design it using flip-flops but with half the frequency of the input clock(Fin). To overcome this issue, I can use a frequency multiplier (Fin*2) , but this solution will increase the complexity of the design.
Is there any other method/way to design Non-Overlapping clock generator (with output frequencies == input frequency).

Thank you.

some frequency is input
and you get four output pulses at the same frequency, that do not overlap one another?

is there a specification for the separation of the output pulse?
or can one have a starting rising edge when another has an ending falling edge?

could you sketch these five signals as a function of time?
 

some frequency is input
and you get four output pulses at the same frequency, that do not overlap one another?

Yes!

is there a specification for the separation of the output pulse?
or can one have a starting rising edge when another has an ending falling edge?

could you sketch these five signals as a function of time?
The output signals should be 45°, 90°, 135°, 180° phase shifted from the input signal.


(This can be achieved using delay elements as mentioned earlier by others; I haven't tried PLL/DLL methods. But again these phase shifts are frequency and technology dependent and not the same for every input frequency. And I'm looking for a general design)
 

And I'm looking for a general design
First time mention. So you should go for PLL. What's your target hardware?
 
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    cb258

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Spartan 6 PLL module can do what you want.
 
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    cb258

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Hi,

from post #6:
could you sketch these five signals as a function of time?
It really would help ... yourself.

Klaus
 

A shift register provides non-overlapping pulses. It's made from D flip-flops (as you first mentioned). Classic digital logic. Works at any clock frequency. No capacitors.

No time constant adjustments. This is not a chaser circuit (as in post #5).

shift register 4 D flip-flops make non-overlapping pulses.png

Of course the initial clock needs to be a higher frequency. Is that a major problem?
Notice you can make 5 stages. That way you have 4 pulses identical to the first pulse, exactly what you require.

The invert-gates may not be necessary in real life. I found they tend to create stable behavior immediately as the simulation begins.
 
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Hi,

That way you have 4 pulses identical to the first pulse, exactly what you require.
Not exactly.
It gives output signals: 0°, 90°, 180°, 270°
But OP wrote:
The output signals should be 45°, 90°, 135°, 180° phase shifted from the input signal.

My initial assumption was 0°, 90°, 180°, 270°, too, each with 90° of pulse width.
OP sadly does not give any pulse width requirement (besides "non overlapping") and does not want to draw a clarifying sketch...

Klaus

Btw: I recommend to use: D1 = /Q1 ^ /Q2 ^ /Q3 ^ Q4
 
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    cb258

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Not exactly.
It gives output signals: 0°, 90°, 180°, 270°
But OP wrote:
The output signals should be 45°, 90°, 135°, 180° phase shifted from the input signal.

I noticed, but must confess, I didn't care for the details of the specification, obviously it's either erroneous or incomplete (very small pulse width).

Anyway you need a PLL to generate any similar pulse pattern if you can't rely on delay elements or want variable frequency. If you use it, the pulse pattern is just a matter of programming.
 
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    cb258

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could you sketch these five signals as a function of time?
Here's the output signals sketch. (Ofcourse, the risetime and falltime are not considered here)
Untitled Diagram.jpg
 

Hi,

Your sketch:

Your initial requirement was "non overlapping"
In my eyes the HIGH signal of output1 overlaps the HIGH signal of output2 by 75%.
So it's rather a 3/4 overlapping signal than a "non overlapping" signal.

--> please refine your requirements.

Klaus
 

O.k., wrong specification, but generation method is essentially the same. I think, the original question has been answered, any additional problems?
 

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