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[SOLVED] Using 2 push buttons to light LEDs

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chandlerbing65nm

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I have a problem with turning on the LEDS using push-buttons. The LED (1 or 2) only tuns on when I both push-buttons (long press pb1 , quick press pb2 to light LED 2 and long press pb2 , quick press pb1 to light LED 1).

The code is written in verilog.

Here is the Top level block:
Code:
module debouncer(
input [1:0]pb,
input clk,
output [1:0]score);

wire slow_clk;
wire Q1,Q2,Q2_bar;
reg [1:0]pb_out;

clock_div u1(clk,slow_clk);

my_dff d1(slow_clk, pb,Q1 );

my_dff2 e1(slow_clk, Q1,Q2 );

assign Q2_bar = ~Q2;

always @(pb) 
	begin
		if (pb[0] == 1'b1) begin
			pb_out[0] <= Q1 & Q2_bar;
			end
		else if (pb[1] == 1'b1) begin
			pb_out[1] <= Q1 & Q2_bar;
			end
		else begin
			pb_out = 0;
			end
	end

assign score = pb_out;
		

endmodule

The clock divider code:
Code:
module clock_div(input clk, output reg slow_clk

    );
    reg [23:0]counter=0;
    always @(posedge clk)
    begin
        counter <= (counter>=1250000)?0:counter+1;
        slow_clk <= (counter < 625000)?1'b0:1'b1;
    end
	 
endmodule

The DFF code:
Code:
module my_dff(
input DFF_CLOCK, 
input [1:0]D, 
output reg Q
);

always @ (posedge DFF_CLOCK) 
begin
	if (D[0] == 1'b1) begin
		Q <= D[0];
		end
	else if (D[1] == 1'b1) begin
		Q <= D[1];
		end 
	else begin
		Q <= 1'b0;
		end
end

endmodule

module my_dff2(input DFF_CLOCK, D, output reg Q);

    always @ (posedge DFF_CLOCK) begin
        Q <= D;
    end
endmodule
 

So where is your testbench code to verify the code above, before you loaded it on your FPGA board?
 

Here is the compressed version the overall code:

Code:
module debouncer(
input [1:0]pb,
input clk,
output [1:0]pb_out);

reg slow_clk_en;
reg Q1,Q2;
reg Q2_bar;
reg [23:0]counter=0;
reg [1:0]score;  
  
always @(posedge clk)
    begin
     counter <= (counter>=1249999)?0:counter+1;
     slow_clk_en <= (counter < 624999)?1'b0:1'b1;
    end
  
always @ (posedge slow_clk_en) begin
	if (pb[0] == 1'b1) begin
           Q1 <= pb[0];
			  Q2 <= Q1;
			  Q2_bar <= ~Q2;
			  score[0] <= Q1 & Q2_bar;
			  end
	else if (pb[1] == 1'b1) begin
				Q1 <= pb[1];
				Q2 <= Q1;
				Q2_bar <= ~Q2;
			   score[1] <= Q1 & Q2_bar;
				end
	else begin
				Q1 <= 1'b0;
				Q2 <= Q1;
				end
end

assign pb_out = score;

endmodule
 

Test Bench waveform from fpga4student.com not working

Hi folks,

I tries to simulate the code and testbench from fpga4student.com and my waveform is not similar to the waveform given by the website, I don't know the problem. All the codes that I used is the same with what the website posted.

Here is the waveform that I got:
debouncer.PNG

And here is the waveform of the website: refer to the bottom image of the website
https://www.fpga4student.com/2017/04/simple-debouncing-verilog-code-for.html
 
Last edited by a moderator:

I asked previously where is your testbench?

If you want the push buttons to independently turn on/off a corresponding LED, then why do you have the code to generate score (i.e. pb_out) in the same if-else if block and Q registers being shared between the two LED push button controls?

Inspecting you latest version of the code your implementation isn't a debounce it is more of a sampled input with an edge detect pulse output that sort of behaves like a debounce circuit under a limited set of conditions. An debounce circuit should reject all inputs that aren't stable for a given amount of time (usually in the 10s of milliseconds for switches) and passes the input to the output once the signal is stable for that amount of time.

- - - Updated - - -

Hi folks,

I tries to simulate the code and testbench from fpga4student.com and my waveform is not similar to the waveform given by the website, I don't know the problem. All the codes that I used is the same with what the website posted.

Here is the waveform that I got:
View attachment 158250

And here is the waveform of the website: refer to the bottom image of the website
https://www.fpga4student.com/2017/04/simple-debouncing-verilog-code-for.html

You aren't running the simulation long enough to count out the 1.25 million clock cycles of clk so aren't doing any of the "debouncing".
 
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