# Data rate between components connected through AXI

1. ## Data rate between components connected through AXI

Hi,

I'm thinking of a project for an FPGA from Xilinx, where the camera data will be saved to the BRAM. I've got to calculate the buffers and other interfaces.
The camera interface with FIFO and BRAM will be connected to AXI Smartconnect component. In case of a 100 MHz clock, what data rate can I expect when writing and reading from BRAM?

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2. ## Re: Data rate between components connected through AXI

You didnt specify the interface. But a lot of this depends on all sorts. In theory you can get 100,000,000 * bus width bits per second from a BRAM, but alot will depend on the turnaround and pipelining of the AXI transactions.
Basically, you need to provide more detailed information.

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3. ## Re: Data rate between components connected through AXI

The preliminary informations that I have are that the camera capture system will be on Kintex 7, which has around 11.4 Mb BRAM. The camerahas 2048 x 2048 pixels and 10 bits per pixel. Some of my calculations are:

1. Camera has an output clock 120 MHz.

2. Camera has 16 data lines, every line is transmitting 128 pixels (x 10 bits = 1280 bits) in a burst => so one such a burst on all lines is 2048 pixels (one of 2048 rows).

3. RAM has XX Mbps write rate.

4. So writing 16 bits (from 16 lines) to FIFO takes one clock cycle = 1/120 MHz = 8.33 ns

5. Writing whole burst will take 8.33 ns * 1280 (burst length) = 10667 ns

6. On the other side memory is getting data with XX Mbps -> XX MHz -> one bit is 1/XX MHz = YY ns.

7. I can assume some BRAM writing rate: 200 Mbps, so it is 1/200 M = 5 ns per bit.

8. So in the time of writing whole burst to the FIFO we have 10667/5 = 2133 bits written to BRAM.

If the one burst has 1280 * 16 lines = 20480 bits and in the meantime memory can get 2133 bits, FIFO buffer has to store remaining 18346 bits ~ 18 kb

Then I have to make similar calculations for the data that is read from BRAM by the Processing Unit. But now I'm not sure how much data should be passed in one burst to the Processing Unit. Maybe the first assumption will be that most algorithms are working on row by row, so those 20480 bits have to be passed from BRAM to PU.

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4. ## Re: Data rate between components connected through AXI

In an FPGA, you can usually process the data at pixel rate, so unless you need to synchronise to a video output, you dont need to buffer the whole frame. Probably just a few lines.

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