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Ideal switched capacitor circuit - voltage spikes

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Ata_sa16

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Hi all,

I am trying to simulate 1.5 bit ADC stage (switched capacitor topology).

I used ideal components. I am getting the correct plot; however, I have voltage spikes at the output (Kv level).

I tried to add parasitic capacitance to make switches little bit realistic but it does not work.

I am attaching all plots. Thank you for your time and effort.


I figured out that my switch turns on when v=1 so something happens between 0-1. I fixed the problem with lowering switch threshold to 0.5
This does not let vout rise during clock transition. I am trying to find out why this happens ...



adc1.PNG
output.PNG
output_zoomed.png
output_spike.png

ideal switch
ideal_switch.PNG


After making threshold vclose = 0.5

fixed.PNG
 
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I am too lazy to calculate.
What has bigger impact - gain of vcvs or rise time of clocks?
If gain (gain of vcvs is 1M, cap divider is 1m product is 1k) decrease gain
If rise/fall time of clocks, make them longer
 
I am too lazy to calculate.
What has bigger impact - gain of vcvs or rise time of clocks?
If gain (gain of vcvs is 1M, cap divider is 1m product is 1k) decrease gain
If rise/fall time of clocks, make them longer

I will decrease the gain that should help. But in calculations we need a very high gain since we assume ideal system.

I made longer rise and fall it does not help. Vout starts peaking as soon as p2 clock starts to rise.
 

I'm not sure whether is possible to remove discontinuity using relay element.
If you need ideal system for behavioral modeling, why not write VerilogA module for mdac?
 

I cant write verilogA for the whole system it is too much. I am not very good with verilogA
I wrote a code for only switch and it does not converge for some reason.
 

There's such a thing as "too ideal".

Switch elements in SPICE/Spectre are notorious for
transient convergence problems. Imposing an infinite
slew rate on a circuit without capacitances leads to
absurdities, which doesn't play well.

You can write (or shoplift) a veriloga switch macro
that has finite transition times, finite on and off
resistances. You could put trivial capacitors and
conductances from key nodes to ground. There
is a "transition" feature of veriloga (forget the
syntax, but find it often in veriloga digital gate
primitives).
 

There's such a thing as "too ideal".

Switch elements in SPICE/Spectre are notorious for
transient convergence problems. Imposing an infinite
slew rate on a circuit without capacitances leads to
absurdities, which doesn't play well.

You can write (or shoplift) a veriloga switch macro
that has finite transition times, finite on and off
resistances. You could put trivial capacitors and
conductances from key nodes to ground. There
is a "transition" feature of veriloga (forget the
syntax, but find it often in veriloga digital gate
primitives).

I did this already to my switch.

First of all you can define open and close resistance to your switched.
I also added capacitance (Cgd - Cds - Cgs)
still same problem.

- - - Updated - - -

Adding capacitors and making Ron=50 Roff = 1 MEGA

2.PNG

1.PNG
 

If I understood properly, gain in vcvs is important.
Try to use svcvs element instead of vcvs.
Svcvs is vcvs with Laplace transfer function, so you can implement 1st order opamp using it (remember that pole should be negative and is in rad/s).
Second option is to limit output voltage of vcvs - it has min and max value for output, so if you limit it to your full scale, issue might gone.
 

If I understood properly, gain in vcvs is important.
Try to use svcvs element instead of vcvs.
Svcvs is vcvs with Laplace transfer function, so you can implement 1st order opamp using it (remember that pole should be negative and is in rad/s).
Second option is to limit output voltage of vcvs - it has min and max value for output, so if you limit it to your full scale, issue might gone.


I tried. The voltage limit is a good way. It limits spike amplitudes but they are always there.

Whatever I do I cannot remove them.
 

The buety of numerical simulations...
You can try VerilogA, apply some delay in vcvs, try to play with ahdlib blocks or simply use value() function to plot the waveform composed from points excluding these glitches.
What do you do with this waveform? Do you need to perform some math on it, or you need ideal steps to be applied into next stage?
 

I will connect this stage to others to construct pipeline ADC.

Since we produce bits at the output and convert them to decimal manually using a code, it should not be a problem.
voltage spikes wont effect bits I think since they occur for a very short time. (I hope so)

we use final decimal value to do DNL, INL and other stuff. It should be okey but I am worried anyway. Other than that I dont like how it looks honestly :grin:
 
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