Resistor, capacitor and MOSFET corneres relationship

Hello,

In the technology I am working I have the common corners for the MOSFET :

FF, SS, FS, SF

Those corners are clear from me, like FF means fast NMOS and fast PMOS, SS means slow NMOS and slow PMOS, FS means fast NMOS and slow PMOS and SF mean slow NMOS and fast PMOS.

The fast and slow terms I can connect it to the gate oxide thickness and then to threshold voltage variation,

The thing which I don't understand, how in the process the NMOS can be slow and PMOS fast (SF) or the reverse at FS ?

The second important thing for me which I didnt understand yet, for my resistor and capacitor model technology I have only FF and SS, beside for sur the typical mean TT, and I dont know what FF or SS means for capacitor and resistor, I am expecting the FF will make both capacitor and resistor smaller while SS makes them bigger.

My main problem is just right now coming

In the corner simulation, I setting up the process corners for my circuit,
you see that for MOSFET they have four corners beside TT, while for resistor and capacitor they have only two,

A possible solution that I cover all possible corners just like a digital inputs, means that I can have a corner setting like this

MOSFET FF, resistor FF, capacitor FF
MOSFET SS, resistor SS, capacitor SS

For the above table I have no issue. my issue for example like below setting

MOSFET FF, resistor SS, capacitor FF
MOSFET SS, resistor FF, capacitor SS
......
.
.
.
.
............ etc,

mean is it possible to have different condition for every component from other component ? by simulation there is no problem and he accept any combination, but is that realistic combination, I am thinking that such kind of combination might never exists in real fabrication ?


Thank you very much in advance

Best regards

Some corners are in fact unrealistic (FS, SF) as they
will make NMOS and PMOS have discrepant Tox (unless
the modeling folks dug into the FS (say) param set
and ensured that Co-process-modulated params
move in step, not in opposition).

MOS caps ought to track Tox and really ought to be
modeled as MOSFETs. But "cap" may or may not be
MOS cap. Many "analog" flows provide a MIM (or two)
which is entirely unrelated.

Resistors are independent of MOS processing and
can be let to wander as they'd like.

You forgot to include corners for BEOL (for parasitics).

- - - Updated - - -

There are other factors affecting Vt - such as channel implant, gate material, etc. - that are (or may be) different for nMOS and pMOS transistors - in which case SF and FS corners are not unphysical.

Thank you friends for your reply,


this is a clear picture of procees variation with corners and MC



It shows freebirf stated that FS and SF are in fact unrealistic

- - - Updated - - -

dick_freebird said:

MOS caps ought to track Tox and really ought to be
modeled as MOSFETs. But "cap" may or may not be
MOS cap. Many "analog" flows provide a MIM (or two)
which is entirely unrelated.

Resistors are independent of MOS processing and
can be let to wander as they'd like.

Click to expand...

Sorry I didnt get your point reagarding capacitor and resistor, I have simulated resistor and capacitor alone with WS and WP, and it is giving the maximum variation that can be predicted by MC, and it is normal expecgted like to haave 20 % variation change,
My problem is different, let me please address it to you again

I need your answer for this combination if it realistic or unrealistic, Ignore for simplicity the FS and SF critical corners:

MOS Cap(poly) Resistor

FF FF FF
FF FF SS
FF SS FF
FF SS SS
SS FF FF
SS FF SS
SS SS FF
SS SS SS

is it possible for example to have cap with FF while resistor in SS state ?

Thank you

What is the "cap" construction? What (if anything)
does it share with FETs or resistors?

dick_freebird said:

What is the "cap" construction? What (if anything)
does it share with FETs or resistors?

Click to expand...

Thanks for the reply,

Capacitor is poly-poly capacitor and the resistor is poly resistor,

Suppose I am connecting the resistor in series with the capacitor for the compensation,

is there any relationship of that to the process corner ?

thank you once again

I would say that these have no, or trivial relation to
"digital MOS corners" and should be varied independently.