Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Here, I am asking that
After doing sanity check check_timing , we get to know that how many flops are not getting clocks. For that how to trace where the problem is ? and how to resolve it ?
Here, I am asking that
After doing sanity check check_timing , we get to know that how many flops are not getting clocks. For that how to trace where the problem is ? and how to resolve it ?
You have made such a humongous mistake that it should not need any explanation. TRACE THE DAMN LOGIC. FIND WHERE THE CLOCK IS MISSING. How hard is this? Have you actually tried? What is stopping you?
The problem shouldn't be coming to this stage. I would doubt the engineer who wrote the RTL!
How can the person write an RTL such that a clock is not connected to a flop?
Ridiculous. This is not a problem of “un-clocked flops”; it’s a problem of design. How do you know there are “un-clocked flops”? Did you run a simulation? if you put a signal in a clocked process, you’ll get a FF with a clock. How do you even GET a “un-clocked flop”??
If it is a check_timing command then there probably isn't a clock constraint defined for the clock. My guess would be it's a internally generated clock that requires a create_generated clock command to specify it's reference, source node, frequency, and duty cycle.
I think the OP needs to ask the person responsible for the RTL (that has this clock) and someone else with more experience in using DC.
According to dc user manual, check_timing checks for unconstrained clocks (see post #11) and clock gating. Which warnings do you see for the respective FFs?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
