Output impedance of SMPS input filter?

Hi,
Please confirm the impedance “seen” looking into the output of our SMPS input filter?
Our input filter is like the “parallel damped filter” of page 23 of the “DCM design guide”.

DCM design guide:
https://www.vicorpower.com/documents/design_guides/DG-DCM-Design-Guide-VICOR.pdf

…we have
CDM = 45uF
LDM = 1uF
Cd = 47uF
Rd = 1
n = Cd/CDM = 1.04

……The output impedance of this filter is the Rd_Cd branch, in parallel with the CDM branch, in parallel with the LDM branch. (this is because there is considered to be a source at the filter input which, with its big output electrolytic capacitor, is considered to be a short to AC.)
…as our excel sheet shows, the maximum impedance of the output of this input filter is 1.02 Ohms.
However, pg 23 of the “DCM design guide” states that the maximum impedance is Ro * {SQRT (2(2+n)}/n
..where Ro = SQRT(LDM/CDM)
….but this comes out as 0.352 Ohms.

Can we please kindly get a reality check on our circumstances please?

The attached LTspice AC sim and schem seem to confirm our result, against the "DCM design guide" result...would you agree?

Your design doesn't follow the calculation method suggested in the design guide. See page 26f for an example calculation.

They assume n > 1, e.g. 3.2 in the example. If you chose n=1 anyway, optimal Rd comes out around 0.25 ohm, resulting in |Zo,max| of 0.35 ohm.

Thanks, we are unable to follow the design guide method, since we have four vicor DCM modules at the output of a single vicor BCM module, and if we do it their way, then we end up with too high Cd value(s)....and the BCM module wont start up due to having too much capacitance at its output...therefore we are just going to calculate the output impedance of our input filter and ensure it is 10 times less than the DCM module input impedance.

It is mainly the Z of the nearest electro ...

Thanks, in the schem of the top post, C2 is ceramic, C1 is solid polymer electro.....and to the left of the inductor is a 47uF solid poly electro (or rather 4 x 47uF because there are 4 stages in parallel, after the BCM module) ......then the BCM module....which in turn feeds from two series 100uF electros........that will look like a 12.8mF capacitor with extrememly low esr and esL, becuase of the 16:1 transformer in the BCM module

I don't understand what's your present problem. Even the "parallel damped" filter with higher than optimal Rd meets the input impedance specification. If you tune Rd for minimal filter output impedance, it can be further improved.

Your SPICE simulation is of course correct, you get similar results with design guide calculation method, if applied correctly. Although your Cd is and factor n is considerably lower than suggested, it should still work.

You should utilize the advantage of SPICE simulation and add typical ESR to all capacitors.