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RTL design (system/Verilog) for Linked list with buffer/SRAM storage

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sandeepj

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I am looking for a reference design for creating several linked lists pointing to a shared buffer/sram space. Tried to search for papers/ college classes but can't find a reference design.

Basically I have several Input buffer queues, storing requests: e.g. 6 Queues, with 10/3/8/32/16/64. Linked list points to a sram for storing queue entries. Queues will be served by arb.
I am looking on how to code in rtl for these queues & build a Roundrobi arb.
 

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