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Question why one of the MOSFET burn shorted in my SS relay

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The complete ckt is not shown, the SSR is in series with a power supply and load, the loop area of this total connection has inductance

showing the Vds at turn off may well shed light on the failure mechanism ...
 

The complete ckt is not shown, the SSR is in series with a power supply and load, the loop area of this total connection has inductance

showing the Vds at turn off may well shed light on the failure mechanism ...

I don't know how to measure the waveform of the Vds as the whole circuit is floating on the amplifier output signal. It is just a simple relay connect between the amplifier and the load. The purpose is to disconnect the load from the output of the amplifier if there is a DC voltage exceed 1V and also disconnect the load during power on and power off to prevent any pop during the power up and power down.

As described, The drain of Q14, Q17 and Q32 is connected to the load. The Drain of Q13, Q16, Q31 are connected to the output of the amp and is following the signal of the amp. It can be from +32V to -32V.

The best I can do is to attached the schematic of the output stages of the amp including the SS relay in question. The load is connected to J3, J9 and J10. The return is connected back to the ground plane of the PCB.

I hope this helps.

Alan
 

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Hi,

0.5cm to 100cm is a factor of 200.
With a proportionality the inductance should go down from 1300nH to 6.5nH, but it goes down to 283only.
It's not even a factor of 5. And not even close to 200.
Nothing else I did say: While the resistance follows proportionality rule, the inductance does not.

still have inductance, but is as low as I can make it based on limitation of the size and being 2 layers copper.
As I already said in post#2 ... there is more inductance than just the PCB inductance.

Klaus
 

Hi,

0.5cm to 100cm is a factor of 200.
With a proportionality the inductance should go down from 1300nH to 6.5nH, but it goes down to 283only.
It's not even a factor of 5. And not even close to 200.
Nothing else I did say: While the resistance follows proportionality rule, the inductance does not.


As I already said in post#2 ... there is more inductance than just the PCB inductance.

Klaus

Yes, the inductance does not follow like the resistance. It's similar to the size of the wire vs inductance. That's the reason using 6 of 16 gauge wires in parallel is much better than using a 8 gauge big wire and that's what I did on the wiring as shown in the second picture in post#16.

I believe the MOSFET failed when I was having 24000pF connected between the + and - in the picture in post#16. I did have a RC across the + and - also, it's 0.1uF in series with 5ohm 3W metal film resistor. So you see the whole circuit.



BUT anyway, I don't want to go too deep into inductance as this is only one of the many unknown in this case. I'm sorry that I keep hoping on the problem because this is the first failure in 4 years, the next one might be a long time. So it's all theoretical discussion here. I am hoping to gather all the input and do a blanket fix and see.

So far, I learn from here.

1) rise time of my circuit is too slow, I need to speed it up by changing R4 and half the rise time shown in post#8. Slow rise time might give enough time in the "in-between" region that SOA comes into play.
2) Do NOT reuse MOSFET taking out from an old board!!! ( that was stupid on my part). But I only did that on the protoboard, so that might not be a real issue.
3) I still think there's a possibility of MOSFET self oscillation as describe in the post #1. Seems like none of you guys think that.

Thanks a lot

Alan
 

If you can show the G-S waveform, as in your earlier post, then surely you can show the D-S waveform at turn off - just make sure the scope ground and the amp power supplies do not have any other common connection.
 

If you can show the G-S waveform, as in your earlier post, then surely you can show the D-S waveform at turn off - just make sure the scope ground and the amp power supplies do not have any other common connection.

I have to think about how to measure and set it up.

I cannot do a simple scope probe test like the other one. In post#8, I actually built only the small section to take the picture. I actually connect the ground of the probe to the source and measure the gate with no amplifier driving. That is the ground of the probe to the S and measure the G. That will not work in the real condition where the amp is actually driving a signal through. If you look at the circuit, you can see the output of the Amp is connected to the D of Q13, Q16 and Q31. When the SS relay is on, the D and S are shorted together and the ground of the scope with short out the output of the amplifier. I checked the scope, the return of the scope probe is earth grounded, so I cannot just hook the ground onto the S.

The only way is to use differential measurement. ie using both channel 1 and channel 2 of the scope to hook onto the D and G resp and use (Channel 1)-(Channel 2) to get the waveform.( On the scope is inverting one channel and add them together). But I won't have a ground reference. The other way is to isolate the earth ground of the scope and let the whole scope float with the output of the amp. I am not comfortable with that. I am in the middle of modifying one of the pcb to decrease the rise time and put gate resistors to everyone of the FET, so I have to wait until I finish before I can do this. Maybe tomorrow.





BTW, what are you looking for with this test? Are you worry about Vds goes beyond the maximum of the MOSFET?

If so, I doubt that will kill the FET that quiet and easy as I explain in post#14 in detail: That I have experience in pushing the Vds beyond the limit and they just zener and it's not like the moment it goes beyond the Vdsmax, it will just die. There is also a body diode that conduct when the polarity of the Vds goes in opposite direction.
 

If you can show the G-S waveform, as in your earlier post, then surely you can show the D-S waveform at turn off - just make sure the scope ground and the amp power supplies do not have any other common connection.

Can you tell me what are you looking for?

I gave it a lot of thoughts in how to measure the Vds when switching, it's just not possible to do because I don't have a digital scope that can record a totally random event particular pre-trigger. The reason is in the real test, there a two totally random events, 1) the switching signal for the SS relay ( MOSFETs), 2) the output signal of the amplifier.

To complicate this matter, I gate the amplifier signal to prevent overheating of the amp. That complicates even more. Even if I manage to create 3 trigger signal, the event is NOT going to be random and it will not really tell the whole story.

Let me know what you are really looking for first, and at the mean time, I have to think whether I am willing to spend $500 for this test. This is my home hobby, not a company problem. I found it a lot more useful to have a 400MHz old analog scope than a fancy 100MHz digital scope. This is the first time I ever run into needing a digital scope. So I have to think seriously before I spend the money.

Thanks.
 

use differential measurement, using both channel 1 and channel 2 of the scope to hook onto the D and G respectively and use (Channel 1)-(Channel 2) to get the waveform.( On the scope is inverting one channel and add them together)

this should be pretty easy - trigger at 35V ... turn up the brightness / persistence to see fleeting effects ...
 

use differential measurement, using both channel 1 and channel 2 of the scope to hook onto the D and G respectively and use (Channel 1)-(Channel 2) to get the waveform.( On the scope is inverting one channel and add them together)

this should be pretty easy - trigger at 35V ... turn up the brightness / persistence to see fleeting effects ...


I know, that's the easy part, the trigger and capture the wave form is the difficult part as I explain in the last post, I have a random signal from the amp that drive the SS relay. So if I take the picture, I will get a smear on the signal. I also have to gate the signal to the amp on and off to prevent the amp from over heat as I am driving signal at clipping level. That's the way I test when it failed.

That's why I want to know what you are looking for and what is so critical. I spent hours thinking about how to set up, there's just no way to do it until I have a digital scope. I even talking about channel1-channel2 in the last post, that's not the problem.

Now, I am not totally ruling out spending the $400 for the digital scope, I even have a scope picked out this morning:

https://www.amazon.com/Siglent-Technologies-SDS1202X-Oscilloscope-Channels/dp/B06XZML6RD/ref=sxin_2_ac_d_pm?ac_md=5-2-QmV0d2VlbiAkMzAwIGFuZCAkOTAw-ac_d_pm&crid=2J74H62JHR55N&cv_ct_cx=oscilloscope&keywords=oscilloscope&pd_rd_i=B06XZML6RD&pd_rd_r=2b4e7424-5b29-4543-a7d7-1e8ff701923e&pd_rd_w=Ydv3B&pd_rd_wg=KlulM&pf_rd_p=0e223c60-bcf8-4663-98f3-da892fbd4372&pf_rd_r=AWTA8ANS38A7THA3XB7R&psc=1&qid=1583895070&sprefix=oscillos%2Caps%2C233

I just want to know exactly what's in your mind that it's so important. If I agree with your idea, I will buy the scope. I really want to get to the bottom of this.

Please tell me what are you looking for.

Thanks.

Alan
 
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If we are to believe your earlier posts - you have already captured the G-S turn on - so it is difficult to see the issue here. As stated above set the rigger to +35V rising to capure the D-S turn off - turn up the brightness so you see everything - and then you can sketch it if you have to ...
 

If we are to believe your earlier posts - you have already captured the G-S turn on - so it is difficult to see the issue here. As stated above set the rigger to +35V rising to capure the D-S turn off - turn up the brightness so you see everything - and then you can sketch it if you have to ...

I tried to explain the best I can in detail. I can assure you it's not possible to get any meaningful image with what I have. Like I said, the original pictures of G-S is very easy because I don't have another random signal and also I don't have to have a gate signal for the amplifier. To take the real picture with the real signal, I have to sync 3 signals together and even if I can, it's NOT random. Believe me, I know what I am doing with the instrument and I spent a lot of time thinking about this already. I even willing to pay $400 for a new scope if I think what you suggest is useful.

Not just the money, I have to remove the board from the heatsink ( 18 big transistors with heatsink compound) in order to modify the board to do the experiment. I just want to know what am I looking for first. I am not a student or a hobbyist, I've been a working EE for over 30 years. If I know what you are looking for, I might be able to do it in an easier way.

Tell me what are you looking for first before I really go through the trouble.

Thanks




- - - Updated - - -

OK, this is the simplified block diagram.

A) is the original setup to take the picture of the Vgs. It's just a small relay and looking at the control signal with NO other signal. It's easy to measure.

B) This is the setup I experience the failure, this is the complete setup.
i) I have to gate the signal generator to get very small duty cycle burst of signal to drive the amp to prevent the amp from overheating.
ii) I have to drive the relay with a signal.
iii) I have to sync up the gate signal of the signal generator and the relay. Even at that, the signal generator always start at the same point, it's not random.

This is the setup I have a failure, it's driving a 24000pF. If I don't gate the signal, the amp will over heat and if using high frequency, the 24000pF will smoke. This is high power as I drive all the way to clipping and beyond.

I have 3 signal generators to generate all the signals, BUT, the analog signal being gated always start at 0V at the same point every time, it is not going to create the real random signal being gated on and off to look at how the Vds behave at different point.

If only I know what you want to see, I might be able to simplify the set up. That's why I need to know what you are looking for.

SS relay testing.jpg
 
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The amplifier has no output current limiting, I presume it's able to destroy a switch transistor under circumstances, either by exceeding SOA characteristic or avalanche energy limit with load inductance.

If the 24 nF load is only an extreme test and not expectable in normal operation, I won't think about the problem that much. If you want safe behavior with any kind of load including short circuit, additional protection means are probably necessary.
 

The amplifier has no output current limiting, I presume it's able to destroy a switch transistor under circumstances, either by exceeding SOA characteristic or avalanche energy limit with load inductance.

If the 24 nF load is only an extreme test and not expectable in normal operation, I won't think about the problem that much. If you want safe behavior with any kind of load including short circuit, additional protection means are probably necessary.

Thanks for the reply. Yes, the 24000pF is for extreme test only. But it failed under this circumstances. That's why I keep talking about this.

Yes, I have a suspicion you hit it on the nail on the turn on time, it's slow. I speed it up and reduce it to half the time already. I have been looking for a better isolator, problem is this ASSR-V621 is a Photovotiac device, not just a phototransistor, choices are very limited. If you have a better circuit than what I have, I am all ears.

I am just paranoid, I want to make sure I cover all bases, then do one revision and be done with it.

Thanks

- - - Updated - - -





If we are to believe your earlier posts - you have already captured the G-S turn on - so it is difficult to see the issue here. As stated above set the rigger to +35V rising to capure the D-S turn off - turn up the brightness so you see everything - and then you can sketch it if you have to ...

I drew up the analysis on the worst case voltage across the MOSFET (Vds). I assume the voltage on LOAD is opposite max and OUT is at max. I should the leakage current path and show the voltage at the D and S of both transistor. The leakage path always go through the BODY diode of the MOSFET ( DQ1 and DQ2).

Also, I show D1.....D4 that prevent any inductor kick beyond the +/-33V. This shows the MAX Vds is only about 66V in all circumstances, way within the spec of the transistor of Vds=100V.

SS relay analysis.jpg

If that's what you are looking for, I don't need to do the measurement, it's guaranty by design already.

Thanks
 
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Since there is no further suggestion, this is what I am going to do:

1) Change out all the re-used MOSFETs to new ones.

2) Reduce R4 from 5.1K to 2.5K ( by parallel another 5.1K) to speed up the rise time. The fall time si less than 20uS as shown in pictures. So I don't think turning off is an issue.

3) I add a 68ohm resistor in series with each of the MOSFET right at the G pin to minimize parasitic inductance.

I don't think Vds of the MOSFET is an issue by design by the explanation in the last post. I am even thinking about using 80V MOSFET because it's cheaper and lower Rdson. It's guaranty by design the Vds will never pass 68V no matter what. 80V MOSFET is plenty already. I have clamping diode D1.....D4 to ensure the voltage never goes 0.7V beyond +/-33V, so max Vds is less than 68V no matter what.

Thankyou guys. I am going to leave this thread open and if there is anything, I will come back.

Thanks
 

Hi,

there are several issues that has been discussed but I'm not sure if you really tested it.

In your posts I see many "I think ..." or "I don't think"...or similar phrases.

Speaking for me, if I say "I think" this means "I am not sure" or in other words "I don't know".
In my work I have to troubleshoot a lot of issues every week. And for every item I am not sure I first try to find a 100% answer. This might be a measurement, a calculation, a check in the datasheet...

In your thread - for me - several things are not 100% sure.
Some of those things ... I don't want to ask again...

But one thing I still wonder is the fall time of the V_gs. You showed a scope picture and you told us several times that the fall time is very short. But according your circuit I find no explanation why it should be that short. I expect it to be slower (more time) than the rise time.
Do you have an explanation why it is that fast?

Klaus
 

I have clamping diode D1.....D4 to ensure the voltage never goes 0.7V beyond +/-33V, so max Vds is less than 68V no matter what.
You wrote about missing clamping diodes in post #3 which brought up avalanche breakdown as possible scenario. If the diodes are in place and properly wired, I would exclude this failure mechanism.

Looking to the TK72E12N1 datasheet, I see a single pulse SOA limit of 30V/40A for 10 µs. According to the reported parameters, it might be exceeded when disconnecting the capacitive load.
 

Thanks for the reply

If you look at the datasheet I linked in post#1, ASSR-V621 has a build in turn off circuit. I have no idea how they do it. But from the waveform picture I took, it is true, it's less than 40uS fall time.

Yes, I am not 100% sure about anything, I failed once in 4 years. I have a few amps that use this circuit, just once. So I can only theorize and make the education guess. I have to put it in to test it. I am still waiting for the new MOSFET to come in on Monday.

To every suggestion I got here, I do spend the time to think and analyze and judge whether it make sense or not, It's like the slow turn on and off time suggested by FvM, it make sense. The suggestion not to rework the FET to avoid failure make sense, that's why I removed all the salvaged FETs and ordered new ones to put in. I myself have experience of FET self oscillation, so I put in the gate resistors. That's the best guess.

Also, I was doing a very harsh test when it failed, I was testing the stability of amps. The amp was on the edge of oscillation with 24000pF right on the output connector. People talked a lot about testing stability using capacitor. BUT most tested with capacitor connect to the output of the amp THROUGH A CABLE. You can hang like 1uF or more without running into stability issue if you connect the capacitor by a few ft cable. The series inductance isolate the capacitance from the amp. Put it in another way, the famous Stasis amp design by Nelson Pass start oscillating with just 1500pF capacitor connecting directly to the output connector without any cable!!! Oscillation is in 500KHz to 1.5MHz range. If you let it oscillate, things will burn, power supply will trip. So current must be really high.

For high end amps, it has to have very very low output impedance and be able to drive a lot of current. I shorted the output accidentally one time while there's signal, it sparked and actually burn a spot on the gold plated connector. Any current limiting circuit will affect the sound as it's always NFB and it will affect the signal. If you look at some high end amps like Krell, they don't put protection circuit. You burn, you burn. That's the price to pay.

So the best is for me to put the modification in, then test the amp just like what I usually do and see.

To be honest, if I have to bet, I still put my money on the oscillation. I've seen many MOSFET die from oscillation, you cannot see on the scope, it's too fast and too short. It died quietly, no fan fare, just die cold. The lead inductance and the Cgs and Cdg form a tank circuit and oscillate, the voltage can exceed the max Vgs and kill the FET quietly and fast. So even though nobody here talk about this, I put in the 68ohm resistor to each of the gate very close to the gate. That should stop the oscillation.

We'll just have to see. To me, this is not blind guessing, it's educated guess. Like I gave a lot of thoughts on the suggestion of monitoring the Vds, I ruled that out because it's guaranty by design to be safe already. I even consider using 80V MOSFET because there's no way Vds will go above 68V.

Thanks

- - - Updated - - -

You wrote about missing clamping diodes in post #3 which brought up avalanche breakdown as possible scenario. If the diodes are in place and properly wired, I would exclude this failure mechanism.

Looking to the TK72E12N1 datasheet, I see a single pulse SOA limit of 30V/40A for 10 µs. According to the reported parameters, it might be exceeded when disconnecting the capacitive load.


Yes, that was my mistake, I make it a point to put the diode in. I just forgot on this particular board. I just notice the diode was missing after the FET burned.

I'll reply to you in more detail tomorrow with datasheet. I use better MOSFET than the TK72, the schematic is a little old. I'll post that tomorrow. It's almost 3am here!!! Time to go to bed.

Thanks
 

Actual turn-off time can't be watched in your waveforms. It's surely short due to active discharge circuit but possibly not fast enough to keep SOA rating when disconnecting high currents.

Consider that the miller plateau in the Vgs waveform respectively the Vds risetime is indicating the interval of high power dissipation, it should be measured with load resistance and maximal output voltage.
 

Actual turn-off time can't be watched in your waveforms. It's surely short due to active discharge circuit but possibly not fast enough to keep SOA rating when disconnecting high currents.

Consider that the miller plateau in the Vgs waveform respectively the Vds risetime is indicating the interval of high power dissipation, it should be measured with load resistance and maximal output voltage.

Good morning

This is the MOSFET I just bought. They are both 100V but much lower Rdson :

https://www.mouser.com/ProductDetail/757-TK2R9E10PLS1X

This is the one I am using and one of this blown:
https://www.mouser.com/ProductDetail/Texas-Instruments/CSD19536KCS?qs=sGAEpiMZZMshyDBzk1%2FWiw3ktwnhg7wCabYHfJTF4q7FiwdiMsVDFQ%3D%3D


Why is turn off time more important? I thought turn on time is just as important as one transistor can turn on first and you can have high current surge. The signal is always on from the amp and it can still give a shock to the MOSFET. I must be missing something, can you explain?

Thanks
 

I was simply assuming that the solid state relays will never be turned on while a larger output voltage is present by working of the protection circuit. If this happens though with low impedance load, there can be a much higher energy dissipated due to the relative slow turn on and SOA exceedance is more likely.
 
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