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  1. #1
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    problem moving from SLL to shift_left in ISE 14.5

    Greetings ... tell you that a couple of days ago I am going through a VHDL project made in Vivado 2017.3 to ISE 14.5. Several of these sources had vhdl 2008 syntax that ISE does not recognize, I could correct some of them, but I am having problems passing the SLL operator of VHDL 2008 to its equivalent shift_left in VHDL 93.
    I leave attached the lines of the original code and the equivalent.

    VHDL 2008

    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    library UNISIM; 
    use UNISIM.vcomponents.all;
    
    entity g1_applic_top_vhdl is
      GENERIC (           
        Hotlink_SDMA_Base     : integer := 0; -- Define the first SDMA engine used by HOTLINK instance 0.
        used_engine_mask      : std_logic_vector(31 downto 0) := (X"0000FFFF" SLL Hotlink_SDMA_Base) OR '0'; -- Set 16 bits = 8 Hotlink ports * 2 engines
        used_wbus_chan_mask   : std_logic_vector(25 downto 0) := ("00000000001111111111111111" SLL Hotlink_SDMA_Base) OR '0' -- Set 8 bits = 4 Hotlink ports * 2 wbus_chans	                
      );	
      PORT ();
    VHDL 93

    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    library UNISIM; 
    use UNISIM.vcomponents.all;
    
    entity g1_applic_top_vhdl is
      GENERIC (           
        Hotlink_SDMA_Base     : integer := 0; -- Define the first SDMA engine used by HOTLINK instance 0.
        used_engine_mask      : std_logic_vector(31 downto 0):= shift_left(X"0000FFFF", Hotlink_SDMA_Base) OR '0'; -- Set 16 bits = 8 Hotlink ports * 2 engines
        used_wbus_chan_mask   : std_logic_vector(25 downto 0):= shift_left("00000000001111111111111111", Hotlink_SDMA_Base) OR '0' -- Set 16 bits = 8 Hotlink ports * 2 wbus_chans	                
      );	
      PORT ();
    This change generates the following error.

    Code:
    Architecture behavioral of Entity g1_asa_top_vhdl is up to date.
    Compiling vhdl file "C:/ProgramData/Teradyne/FPGA/ISEProjects/App0x3120VHDLMaster/src/g1_applic_top_vhdl.vhd" in Library work.
    ERROR:HDLParsers:808 - "C:/ProgramData/Teradyne/FPGA/ISEProjects/App0x3120VHDLMaster/src/g1_applic_top_vhdl.vhd" Line 44. OR can not have such operands in this context.
    ERROR:HDLParsers:808 - "C:/ProgramData/Teradyne/FPGA/ISEProjects/App0x3120VHDLMaster/src/g1_applic_top_vhdl.vhd" Line 45. OR can not have such operands in this context.
    Entity <g1_applic_top_vhdl> (Architecture <behavioral>) compiled.
    --> 
    
    Total memory usage is 4566752 kilobytes
    
    Number of errors   :    2 (   0 filtered)
    Number of warnings :    0 (   0 filtered)
    Number of infos    :    0 (   0 filtered)
    
    
    Process "Synthesize - XST" failed
    Someone who can help me with this problem please, thank you in advance.

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  2. #2
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    barry's Avatar
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    Re: problem moving from SLL to shift_left in ISE 14.5

    not sure what you're trying to do here. It looks like you've got a 32-bit value which is shifted and then OR'd with a single-bit '0'. What are you expecting to happen?



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  3. #3
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    Re: problem moving from SLL to shift_left in ISE 14.5

    In vhdl 93 you cannot use generics to set other generics. I suggest you set the defaults to be constants.



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  4. #4
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    Re: problem moving from SLL to shift_left in ISE 14.5

    Thanks for the help ... I tell you that I was able to solve my problem, removing all these operations from OR and SLL, leaving these lines as follows.

    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    library UNISIM; 
    use UNISIM.vcomponents.all;
    
    entity g1_applic_top_vhdl is
      GENERIC (           
        Hotlink_SDMA_Base     : integer := 0; -- Define the first SDMA engine used by HOTLINK instance 0.
        used_engine_mask      : std_logic_vector(31 downto 0) := X"0000FFFF" ; -- Set 16 bits = 8 Hotlink ports * 2 engines
        used_wbus_chan_mask   : std_logic_vector(25 downto 0) := "00000000001111111111111111"  -- Set 8 bits = 4 Hotlink ports * 2 wbus_chans	                
      );	
      PORT ();



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