Understanding the concept of Charge Trapping

I am studying the process of aging in CMOS. I have seen the concept of "charge trapping" multiple times. Can someone explain this concept, and how it affects switching speed?

-Thanks

You can find many references for this but tending to
use terms like "hot carrier effects", "negative bias
temperature instability" (NBTI, for PMOS; PBTI for
NMOS) and you will find a lot of associated info in
radiation effects publications.

Carriers accelerated by vector sum drain, gate to
body / channel potential, will scatter and some will
leave the silicon to embed in adjacent oxides (any
or all of spacer, gate, LOCOS/STI, BOX). Holes or
electrons can be so-accelerated and trapped. The
electrons have a pretty good chance of tunneling
back out, the holes less so. Oxide traps / defects
make things "sticky" in that respect. Carriers that
are trapped near the interface have outsized
influence. Bias conditions will steer carriers toward
or away from the interface, exacerbating or mitigating
the influence.

Trapped charges have the same sort of influence as
charge imposed on the gate electrode, and add to
or subtract from the gate charge / Vgs. You will see
threshold shifts which alter delays. Gross gate charge
flux also induces generation of defects and where
these abut the channel, additional scattering sites
and mobility degradation (k' declines, while delta
VT could help or hurt depending on species).

IEEE Reliability Physics Society and Nuclear and
Plasma Sciences societies have published much
on this area.