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    LDO transient performance enhancement circuit understanding

    For the following LDO circuit, how does the transient performance enhancement circuit sub-block in green color works ?


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    Re: LDO transient performance enhancement circuit understanding

    I tried to replicate the above LDO circuit in LTSpice, but it does not work yet ....






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    Re: LDO transient performance enhancement circuit understanding

    Where is your transient source so you expect a transient response ??
    You have to change VDD by transient STEP PULSE source to achieve a transient response..Otherwise everything is in steady state response so DC ..


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    Re: LDO transient performance enhancement circuit understanding

    For this LDO circuit , I have pretty good transient output voltage V(vout) for a 100k sine input on Vin.

    But it goes very bad when I use 1MEG sine input on Vin.

    Any advice ?







    LDO.asc

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    TEXT 64 32 Left 2 !.lib mosfet_018.lib
    TEXT 344 32 Left 2 !.tran 100u
    TEXT 520 32 Left 2 !;.ac dec 100 1 1g



  5. #5
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    Re: LDO transient performance enhancement circuit understanding

    Why don't you filter the constant-Gm bias circuit? And you have uA consumption, PSRR is strongly frequency dependent, these 2 things together result above. No surprises.
    "Try SCE to AUX." /John Aaron/


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  6. #6
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    Re: LDO transient performance enhancement circuit understanding

    it is consuming less than 300uA , and as I have tried, increasing current limiting resistor R3 value does not really help in improving PSRR.

    Do you have a decent CMOS circuit for filtering the constant-Gm bias circuit ?



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    Re: LDO transient performance enhancement circuit understanding

    I don't have, I only suggest to add capacitors in paralel with the gate-source of M2 and M10. Or add series resistor with the gates, maybe the combination of them. And don't use minimal length for transistors where it is not necessary, that improves PSRR.
    "Try SCE to AUX." /John Aaron/


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    Re: LDO transient performance enhancement circuit understanding

    And don't use minimal length for transistors where it is not necessary, that improves PSRR.
    How is minimal length related to PSRR ?



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  9. #9
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    Re: LDO transient performance enhancement circuit understanding

    What do you think about the following gain margin and phase margin plot ?

    How to move the zero at the high frequency zone to lower frequency range ?





    LDO_gain_phase_margin.asc

    Code:
    Version 4
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    FLAG 432 1280 0
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    FLAG 3536 704 Vout
    IOPIN 3536 704 Out
    FLAG 688 1136 0
    FLAG 704 976 Vref
    FLAG -416 80 Vin
    FLAG 2112 1264 Vfb
    FLAG -272 1248 0
    FLAG 160 1248 0
    FLAG -64 1568 0
    FLAG -272 944 0
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    SYMBOL pmos4 48 128 R0
    WINDOW 123 62 94 Left 2
    SYMATTR Value2 L=0.18u W=6u m=2
    SYMATTR InstName M2
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    SYMBOL pmos4 1488 384 R0
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    SYMBOL pmos4 944 640 R0
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    SYMBOL nmos4 544 1232 M0
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    SYMBOL cap 1936 912 R90
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    SYMBOL res 3456 992 R0
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    SYMBOL res 3456 1376 R0
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    SYMBOL pmos4 1968 688 R0
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    SYMBOL voltage 688 992 M0
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    SYMATTR InstName M5
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    SYMATTR InstName V1
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    TEXT 64 32 Left 2 !.lib mosfet_018.lib
    TEXT 344 32 Left 2 !;.tran 100u
    TEXT 520 32 Left 2 !.ac dec 100 1 1g
    Last edited by promach; 13th March 2020 at 05:48.



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  10. #10
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    Re: LDO transient performance enhancement circuit understanding

    Why does the transient simulation around 10us have a lot of noise ?

    Where is the actual root cause for such deterministic noise at 10us after simulation starts ? And any idea how to eliminate it entirely from the noise source ?






  11. #11
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    Re: LDO transient performance enhancement circuit understanding

    At every low supply voltage moment there is some "noise" on the output. I think it tells that your circuit is unstable at lower supply voltages. Simulate stability with different supply voltage values, check gain and phase margin.
    I guess your transistors are not good for your application. What kind of model are you using?
    "Try SCE to AUX." /John Aaron/


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    Re: LDO transient performance enhancement circuit understanding

    At lower supply voltage such as 2.5V , LDO does not work anymore.

    I am using this mosfet model

    What do you suggest ?

    I am not sure if FreePDK15 model could actually be used with LTSpice

    In this case, I think I need some other mosfet models.



  13. #13
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    Re: LDO transient performance enhancement circuit understanding

    how much is the minimum and maximum supply voltage do you want? choose transistors which are fit for both. or choose a simplier LDO. or if it is for learning purpose simply don't use low supply.
    "Try SCE to AUX." /John Aaron/


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  14. #14
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    Re: LDO transient performance enhancement circuit understanding

    maximum = 5V , minimum = 2.5V

    https://user.eng.umd.edu/~newcomb/co...c180nmcmos.lib also resulted in similar noise issue.



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    Re: LDO transient performance enhancement circuit understanding

    Could you show an open-loop gain plot? It is stability issue, you have to improve stability. You have to find which transistor enters triode region when you apply low supply. And make surre these transistors can operate on 5V.
    "Try SCE to AUX." /John Aaron/



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    Re: LDO transient performance enhancement circuit understanding





    Note: output load capacitance, CL = 1uF

    and changing Vin parameters such as 3.3V to 2.5V , as well as lowering the Vin frequency from 1MHz to below 1kHz do not change the phase margin.
    Last edited by promach; 29th March 2020 at 02:55.



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    Re: LDO transient performance enhancement circuit understanding

    Are you sure above figure is simulated next to 2.5V DC supply? I think we should see some minor changes at least between 2.5V and 3.3V values. Try to plot both on the same figure. Or you could analyse what is the minimum supply which cause significant change in AC behaviour. BTW what do you mean by lowering frequency parameters do not change the phase margin, this is an AC plot?
    "Try SCE to AUX." /John Aaron/



  18. #18
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    Re: LDO transient performance enhancement circuit understanding

    BTW what do you mean by lowering frequency parameters do not change the phase margin, this is an AC plot?
    Look at Vin SINE() parameters



  19. #19
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    Re: LDO transient performance enhancement circuit understanding

    I have uploaded the LDO circuit at https://github.com/promach/LDO

    I have few questions :

    1. Why in the second bode plot (which might be problematic PSRR), gain going up near unity-gain frequency is often a sign of instability ?
    2. Why is there some initial noise disturbance around 10us during start-up ?
    3. What is the purpose of M2 and M26 ?
    4. Could anyone explain the mechanism of transient performance enhancement circuit consisting of M19, M27, M23, M24 and M25 ?
    5. Any suggestion on suitable test circuit for load regulation metric check ?




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    Re: LDO transient performance enhancement circuit understanding

    The desired Vout is 2.2V
    See Vref, R1 and R2

    Iout = 0 , Vout = 3.2V .........

    Iout = 3A, Vout = 2V


    See LDO_max_Iout.zip

    Click image for larger version. 

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