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  1. #1
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    Unbuffered cells and how does it affect timing constraints

    Hi there,

    I've read in the liberty spec that you can add another dimension to the constraint tables (2D setup/hold -> 3D setup/hold)|(1D mpw -> 2D mpw).

    The extra dimension is the output load where you can specify the related_output attribute.

    How does the output load affect the hold and setup time values?

    I haven't seen a lot of documentation on this so if someone could either clear this up or point me a textbook that I can read about modelling the effects of unbuffered outputs for constraint tables I would greatly appreciate it

    Thanks in advance

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    Re: Unbuffered cells and how does it affect timing constraints

    Unbuffered cells have lower and more asymmetric drive
    strength ("buffered" merely means the output is a regular
    inverter or series pair, sinbgle-stack while (say) a nand4
    would have a 4-high NMOS output stack and 4 parallel
    PMOS, so expect HL drive strength to be low and loading
    sensitivity of that transition, high).

    If you've got a ton of slack or a known-light and close-haul
    load then unbuffered.

    There should be a point where the buffered and unbuffered
    show equal delays (@ center PVT, or @ WC - the latter
    being what you'd probably design to) and knowing that
    "crossover point" might let you make off-the-cuff decisions
    about what type to start with.

    But libraries may also make that decision for you; I have
    seen cases where, for example, nand2 is unbuffered but
    nand3 and nand4 are buffered (for the stack-height
    concern).



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  3. #3
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    Re: Unbuffered cells and how does it affect timing constraints

    Quote Originally Posted by janthonym View Post
    Hi there,

    I've read in the liberty spec that you can add another dimension to the constraint tables (2D setup/hold -> 3D setup/hold)|(1D mpw -> 2D mpw).

    The extra dimension is the output load where you can specify the related_output attribute.

    How does the output load affect the hold and setup time values?
    for timing, the 2D tables are related to the input transition and to the output load. I am not sure I understand what the third dimension is. Are you sure it is called output load?
    Really, I am not Sam.



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  4. #4
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    Re: Unbuffered cells and how does it affect timing constraints

    For the third dimension (I'm just reading the Liberty User Guide) and the third variable is
    "related_out_total_output_net_capacitance".
    Here is what the excerpt says:

    Code:
    Create a three-dimensional table template that uses two variables and indexes to model
    transition time and the third variable and index to model load. The variable values for
    representing output loading on the related_output_pin are:
    
    related_out_total_output_net_capacitance
    related_out_output_net_length
    related_out_output_net_wire_cap
    related_out_output_net_pin_cap



  5. #5
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    Re: Unbuffered cells and how does it affect timing constraints

    Quote Originally Posted by janthonym View Post
    For the third dimension (I'm just reading the Liberty User Guide) and the third variable is Here is what the excerpt says:

    Code:
    Create a three-dimensional table template that uses two variables and indexes to model
    transition time and the third variable and index to model load. The variable values for
    representing output loading on the related_output_pin are:
    
    related_out_total_output_net_capacitance
    related_out_output_net_length
    related_out_output_net_wire_cap
    related_out_output_net_pin_cap
    It looks like there are two indexes for input transition, and one index for load.

    I would guess this is somehow an approach to account for the S-shaped curve instead of a perfect transition on the input of the cell. This is commonly seen in liberty files, it's called driver cell or driver waveform.
    Really, I am not Sam.



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