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    The difference between '|' operator and keyword 'or'

    Hi,
    I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
    In most of the always blocks, the keyword 'or' is used, and in if statements, either '|' is used or '||' is used.
    So functionally, what is the difference between the two, and where to use what.
    Last edited by tahirsengine; 26th February 2020 at 10:26.

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    Re: The difference between | operator and keyword or

    Get the Verilog language reference manual IEEE Std. 1800-2017 for free through IEEEGet program: https://ieeexplore.ieee.org/document/8299595

    Review clause 11.3 Operators



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    Re: The difference between '|' operator and keyword 'or'

    Quote Originally Posted by tahirsengine View Post
    Hi,
    I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
    In most of the always blocks, the keyword 'or' is used, and in if statements, either '|' is used or '||' is used.
    So functionally, what is the difference between the two, and where to use what.
    see this: http://www.asic-world.com/verilog/operators.html

    click on logical operators and on bitwise operators. the difference should be clear.
    Really, I am not Sam.



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    Re: The difference between | operator and keyword or

    The only place the or keyword is allowed is inside an event expression to say wait for this event or that event.

    Code Verilog - [expand]
    1
    2
    
    always @(a or b) ...
    always @(posedge clk or negedge reset) ...

    This is in contrast with the boolean logical or || or bit-wise | or operators

    Code Verilog - [expand]
    1
    
    always @(a || b) ...

    which say to wait for the result of the expression to change, not for each operand to change. If a and b were 1, and b changed to 0, the result is still 1 and it would keep waiting.
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


    1 members found this post helpful.

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    Re: The difference between | operator and keyword or

    Quote Originally Posted by FvM View Post
    Get the Verilog language reference manual IEEE Std. 1800-2017 for free through IEEEGet program: https://ieeexplore.ieee.org/document/8299595

    Review clause 11.3 Operators
    Thanks for replay.

    In Section 9.4.2.1 of same document:

    The logical OR of any number of events can be expressed so that the occurrence of any one of the events
    triggers the execution of the procedural statement that follows it. The keyword or or a comma character (,)
    is used as an event logical OR operator. A combination of these can be used in the same event expression.
    Comma-separated sensitivity lists shall be synonymous to or-separated sensitivity lists.

    The next two examples show the logical or of two and three events, respectively:
    @(trig or enable) rega = regb; // controlled by trig or enable
    @(posedge clk_a or posedge clk_b or trig) rega = regb;

    The following examples show the use of the comma (,) as an event logical or operator:
    always @(a, b, c, d, e)
    always @(posedge clk, negedge rstn)
    always @(a or b, c, d or e)


    So this is called Event Logical OR operator.




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