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    Why set_max_fanout constraint in design compiler ?

    I've been doing a lot of survey article for fanout for design compiler.
    But for some technology process such as 90nm/.18um , our target library (.db / .lib) has already the settings of max_fanout/ max_capcitance for our design, but in 4x nm process, I can't find the max_fanout in .lib file
    1. Is that the reason for settings ?? (But how to determine the value for different process technology)
    2. Why we still need to set the max_fanout for our design (if our design compiler has already having the default settings) ?
    3. For those high-fanout design, those setting seems only make design compiler run longer and hardly to converge, any suggestion for this scenario ??

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    Re: Why set_max_fanout constraint in design compiler ?

    Quote Originally Posted by willvegapunk View Post
    2. Why we still need to set the max_fanout for our design (if our design compiler has already having the default settings) ?
    whatever drive mechanism is used for an output, it has a current limit. setting maximum fanout
    is forcing you to stay under that current limit.

    by setting the fanout yourself, you are reminded of the restrictions.
    you could reduce it from the default set in the compiler for your design reasons.


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    Re: Why set_max_fanout constraint in design compiler ?

    Thanks for your reply ....
    After hours of survey, I'm not quite sure my current understanding is correct or not.
    set_max_fanout VALUE DESIGN
    - this would constrain all the net's fanout with stricter value e.g. min(VALUE, lib or DC's default settings)
    set_max_fanout VALUE [get_ports all_inputs]
    - this would only constrain my DESIGN's input ports, which restrict the size of cell direct connect with my input ports.



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    Re: Why set_max_fanout constraint in design compiler ?

    Every library has timing models derived from some
    bounding conditions including min and max load.
    The fanout you specify, or the fanout that your local
    setup defaults to, must respect that "box" or you
    will be applying models that don't (potentially) cover
    the circuit realities.


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  5. #5
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    Re: Why set_max_fanout constraint in design compiler ?

    According to my understanding, set max fanout simply controls the number of nodes driven by each output port. It provides the tool with a guideline of how much fixing is still needed. But usually max capacitance is the only thing that matters when the load of a port is considered. Max fanout violation can be ignored as long as max capacitance is satisfied.



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  6. #6
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    Re: Why set_max_fanout constraint in design compiler ?

    max_fanout is a type of DRV, just like max_tran and max_load. It made sense some 20 years ago when you could count the number of gates a std cell could drive. Modern std cell libraries don't care about this attribute, in my experience. It just isn't accurate enough to capture the true transition/load behavior of a cell/applied to a cell.

    in summary, if the .lib/.db you are using has some fanout restriction, use it. otherwise, just ignore this setting.
    Really, I am not Sam.


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