# common mode feedback question

1. ## common mode feedback question

Hello , In the the photo bellow we have a common mode feedback circuit.
Mismatch in currents causes a mismatch in voltages which is amplified and connected to the gates of BIAS pmos transistors on top.
But how exactly it fixes the problem ?
The output of the OPAMP is an AC signal ,its not a constant DC point, how does exactly putting an AMPLIFIED AC signal to the pmos gate solves this problem.We could design this mismatch amplifier to be 30dB gain or 20 dB gain ,both of them will create a different amplitude signal of the gates pmos.

In my intuition i see the transistor as ressistors , so when we have a high voltage on one side then we need to increase the PMOS rds ressitance in order to get a lower output signal. but here we get the same signal to both gates of PMOSES on both sides.so we make the same increase/decrease of output voltate on both sides.

How the mismatch fixing goes exactly?

Thanks.

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2. ## Re: common mode feedback question

The output of the OPAMP is an AC signal
- you are making a big assumption - based on what exactly ...?

3. ## Re: common mode feedback question

Originally Posted by Easy peasy
- you are making a big assumption - based on what exactly ...?
our mismatch votage compared to the Vbias and it goes to an OPAMP.
We do have a DC voltage on the output,but the functionality of an opamp is desighed to be in AC region.

In my intuition i see the transistor as ressistors , so when we have a high voltage on one side then we need to increase the PMOS rds ressitance in order to get a lower output signal. but here we get the same signal to both gates of PMOSES on both sides.so we make the same increase/decrease of output voltate on both sides.so i cant see how it fixes the mismatch.

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4. ## Re: common mode feedback question

functionality of an opamp is desighed to be in AC region
- another assumption

unless the op-amp is ac coupled with a capacitor - it will act down to DC ...

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5. ## Re: common mode feedback question

yefj, you have basic problem with understanding what common mode feedback does. It has no connection to mismatch of currents, CMFB sets/tunes both currents in a way that the main OPAMP will operate in the normal active region, it sets all transistor pairs of the differential circuit to the same desired operating point. If the currents have mismatch it doesn't matter from common mode feedback standpoint, CMFB doesn't amplify the difference, it compares the averege voltage of differential outputs to the referential voltage via an error amplifier.

6. ## Re: common mode feedback question

Yes, you really have to sit and think over the purpose and operation of the CMFB circuit. The signal at the gates of the top PMOS transistors has nothing to do with the differential amplifier output voltage and has everything to do with the output common-mode voltage of the main amplifier. When you take the average of two fully differential voltages, as you do with the two resistors at the outputs of the two source followers, you get as a result their common-mode or average voltage. Then you compare it with a reference and control the top PMOS devices so that you get the desired amplifier ouptut common-mode.

7. ## Re: common mode feedback question

Originally Posted by yefj
Mismatch in currents causes a mismatch in voltages which is amplified and connected to the gates of BIAS pmos transistors on top.
Common mode feedback does not solve this.
Common mode feedback solves mismatch between ID(M3)+ID(M4) and ID(M0).
If there is a mismatch between ID(M3) and ID(M4), there will be offset in the output, but because the gates of M3 and M4 are connected together, there is no way to solve it using CMFB.

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8. ## Re: common mode feedback question

There are 2 types of dc correction

1) DC offset cancellation ---> when ID(M3) is not equal to ID(M4). This needs DC offset cancellation circuit and CMFB CIRCUIT DOES NOT SOLVE THIS

2) Imagine you input dc voltage (both + and - DC level) goes up and down. Then the dc level at the output will move up and down and It can saturate your amplifier.

amplifier's input signs are wrong ---> swap + and -

lest say input common mode increases ---> both currents will increase and pull Mc1 and Mc2 gate voltage down ---> vout will drop (dc level) ---> amplifier senses the DC level (amplifier does not sense AC since there are 2 equal resistances and AC voltage on the amplifier input will be canceled - or basically it is virtual ground ) ---> Gate of M3 and M4 will raise --> current will decrease to the initial point

9. ## Re: common mode feedback question

So we are working stricktly on the DC level with the amplfier.
Why if VOUT+ VOUT- goes down then VOUT goes down strickly by DC level which causes the Vgates on PMOSES to go down, I=k(Vsg-vt)^2
so I decreases the Vout+ Vout- DC goes up.
Thanks.

Originally Posted by Ata_sa16
There are 2 types of dc correction

1) DC offset cancellation ---> when ID(M3) is not equal to ID(M4). This needs DC offset cancellation circuit and CMFB CIRCUIT DOES NOT SOLVE THIS

2) Imagine you input dc voltage (both + and - DC level) goes up and down. Then the dc level at the output will move up and down and It can saturate your amplifier.