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    Netlist is different between schematic and layout

    Hello,

    I have designed simple voltage devider MOS resistor, the circuit is working fine in schematic, with the layout there is no issue, LVS is giving o error. However, in the simulation they are showing very different result, then when I compared the netlist I saw it is different between the schematic and layout, looks like he is mixing between drain and source.

    Is it possible to correct to have different netlist if there is not error in LVS ? is there any way to correct it manually ?

    Thank you

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    Re: Netlist is different between schematic and layout

    what software are you using?
    LVS is an abreiviation i don't know

    if there is a drain source issue, it may be in the footprint of the part for the PWB
    or the connection between the pins of the circuit symbol ad the pins of the PWB footprint


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    Re: Netlist is different between schematic and layout

    I guess you will have to provide more information. Like schematic, netlists, show how different the results are, etc. In a MOS transistor divider, interchanging drain and source shouldn't really be a disaster. And finally, one can expect that the netlist from schematic is different/simpler than the netlist from LVS (or more correctly, the extracted netlist).


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    Re: Netlist is different between schematic and layout

    Regular FETs don't have a difference between D-S and
    S-D electrical behavior. Some asymmetric types do -
    drain-extended and LDMOS for example. LVS rules
    will have "S/D swap" switch which allows or does not,
    this permutation based on what somebody knows
    about whether it is or is not consequence-free.

    Now extracted layout derived SPICE netlists often
    (in more advanced nodes) invoke different model
    sets, for reasons such as parasitics partitioning /
    duplication (extract will catch the "internal" parasitic
    C's which schematic-oriented models might embed
    for the designer's benefit, but then such models end
    up "double counting" the intra-device parasitics).
    There could even be weirdness about units, that
    LVS might deal with but could be carried "unscaled"
    in the extracted netlist, and give you (say) a 1x1
    (centimeter) FET instead of a 1u x 1u. You'd have
    to inspect the netlists for such things. You might
    find clues in the differences between schematic
    based and layout based individual devices' OP
    results (if they're off by factors of 1E8 or 1E12,
    bet on units scaling discrepancy).

    You might need to direct the include-chain to a
    different "head end" that's layout-appropriate, if
    such things are a "feature" of your PDK.


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    Re: Netlist is different between schematic and layout

    Dear friends,

    first I would like to thank you for your reply,

    here is the schematic of the MOS resistor, I am using bulk connected to source for these PMOS based resistor,

    Click image for larger version. 

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    below is the layout implementation of this simple circuit

    Click image for larger version. 

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    I am testing the resistor like shown below, I am sweeping the values of the supply voltages similar way to fully differential amplifier output, the reason is that I am intending to use this resistor as an average resistor for VOC. like the volatge in terminal A is increasing with X and the voltage in terminal B is decreasing with X, the steady state voltage is at X = 0 where the two Vdc are set to 1.65 V. in this test configuration test I am testing both the schematic and the extracted layout circuit to have both plots in the same test.

    Click image for larger version. 

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    you see from the result below how the schematic is accurate, giving a constant resistance for the whole range of sweep perfectly, while for the layout have strange behavioural in the middle. I would always expect some change in the layout result but such a falure for small circuit. This circuit is proposed by different authors in IEEE publication.

    Click image for larger version. 

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    and I also attached the netlist report for your kind investigation

    The last but not the least, I tried the same circuit but by connecting the bulk to the VDD and the circuit is working, however, I would prefer the one with bulk connected to source

    I hope now you can better help me with these details
    and thank you once again



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    Re: Netlist is different between schematic and layout

    Diode. Do you know such device?


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    Re: Netlist is different between schematic and layout

    What will happen if you manually place in the schematic view two reverse diodes from VOC to gnd, the same as avD41_4 and avD41_5 from the extracted view?


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    Re: Netlist is different between schematic and layout

    Dear Dominik,

    Thank you for your answer,

    In fact I didn"t get what you mean by diode and how it is making the schematic simulation is different from the layout ?

    As I have also mentioned before in my post, this problem is not appearing once I connect the bult to vdd rather than tie it to the source

    - - - Updated - - -

    Quote Originally Posted by sutapanaki View Post
    What will happen if you manually place in the schematic view two reverse diodes from VOC to gnd, the same as ?
    Dear Suta,
    I will try this soon in Lab, but what ar purposes of it and secondly where are the "avD41_4 and avD41_5 from the extracted view" you are referring to it

    thanks
    Last edited by Junus2012; 18th February 2020 at 23:26.



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    Re: Netlist is different between schematic and layout

    I am merciful today

    In the schematic netlist you have only mosfets - model of channel below the gate oxide.
    In the layout, your p-channel mosfets are putted in the n-wells, which are an island in the p-substrate. Every n-well forms p-n junction with substrate, modeled by nwd devices added by extractor into netlist.

    In case, when your parameter x is zero, your pseudo resistor has the same 1.65V on terminals VA and VB. Transistors are biased with V_GS=0 - they are completely off.
    I am pretty sure, that leakage of these guys is small. In schematic netlist, there is nothing connected between terminal VOC and gnd, so due to symmetry of structure V(VOC)=1.65 (average of VA and VB).
    However, diodes has some leakage and thus finite resistance, so with completely off mosfets, these diodes pulling down terminal VOC to ground. Moreover, they are providing conditions to bias two mosfets into more cut-off region, changing ratio of resistances seen from VOC to gnd and to VA/VB, additionally decreasing potential at VOC.

    The lesson for you.
    Transistor is not only transistor but whole environment - modern nodes has complicated two or even three level hierarchical subcircuits, taking into account all junctions, contacts and necessary level of metalization. Old technologies like used by you 22 years old AMS C35, usually are not modeled on such deep level. And as you can see, ordinary diodes for n-well to p-substrate junction diodes are added after extraction, not before. Moreover, old models like used here bsim3.3 might has an issues in some extraordinary bias conditions - series connection of cut-off devices is such abnormal conditions (and even J. Baker mentioned about bsim3 issues in one of his book 20 years ago).

    In real, for such conditions with VA=VB, you have transistors with no channels, only diodes, leakage current and potential accumulation region for some of them.
    Basically, your VOC can be considered as "floating node" and can be on whatever potential.


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    Re: Netlist is different between schematic and layout

    Quote Originally Posted by Junus2012 View Post

    Dear Suta,
    I will try this soon in Lab, but what ar purposes of it and secondly where are the "avD41_4 and avD41_5 from the extracted view" you are referring to it

    thanks
    These reverse connected diodes are in the extracted netlist. Just look there, I listed in my previous post the names under which they appear in the netlist.


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    Re: Netlist is different between schematic and layout

    Quote Originally Posted by Dominik Przyborowski View Post
    I am merciful today

    In the schematic netlist you have only mosfets - model of channel below the gate oxide.
    In the layout, your p-channel mosfets are putted in the n-wells, which are an island in the p-substrate. Every n-well forms p-n junction with substrate, modeled by nwd devices added by extractor into netlist.

    In case, when your parameter x is zero, your pseudo resistor has the same 1.65V on terminals VA and VB. Transistors are biased with V_GS=0 - they are completely off.
    I am pretty sure, that leakage of these guys is small. In schematic netlist, there is nothing connected between terminal VOC and gnd, so due to symmetry of structure V(VOC)=1.65 (average of VA and VB).
    However, diodes has some leakage and thus finite resistance, so with completely off mosfets, these diodes pulling down terminal VOC to ground. Moreover, they are providing conditions to bias two mosfets into more cut-off region, changing ratio of resistances seen from VOC to gnd and to VA/VB, additionally decreasing potential at VOC.

    The lesson for you.
    Transistor is not only transistor but whole environment - modern nodes has complicated two or even three level hierarchical subcircuits, taking into account all junctions, contacts and necessary level of metalization. Old technologies like used by you 22 years old AMS C35, usually are not modeled on such deep level. And as you can see, ordinary diodes for n-well to p-substrate junction diodes are added after extraction, not before. Moreover, old models like used here bsim3.3 might has an issues in some extraordinary bias conditions - series connection of cut-off devices is such abnormal conditions (and even J. Baker mentioned about bsim3 issues in one of his book 20 years ago).

    In real, for such conditions with VA=VB, you have transistors with no channels, only diodes, leakage current and potential accumulation region for some of them.
    Basically, your VOC can be considered as "floating node" and can be on whatever potential.
    Dear Dominik,

    It is very helpful and excellent answer and help, I am very sincerely to you for this big effort

    Through your explanation, I now understand that this kind of resistor can not work with equal voltages at the terminals, however, still one question in my mind which you forgot to answer me, what is the thing that made it work perfectly when I connect the bulk to the VDD rather than to the source.

    Below I would like to share you circuit images of some famous publication, for them they connected the source to the bulk and having no issue, is the condition in their circuits are different ?

    Click image for larger version. 

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    Click image for larger version. 

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    Click image for larger version. 

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    Thank you once again

    - - - Updated - - -

    Quote Originally Posted by sutapanaki View Post
    These reverse connected diodes are in the extracted netlist. Just look there, I listed in my previous post the names under which they appear in the netlist.
    Dear Suta,

    Thank you for your continuous help,

    I tried it but couldnt work



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    Re: Netlist is different between schematic and layout

    Quote Originally Posted by Junus2012 View Post

    Dear Suta,

    Thank you for your continuous help,

    I tried it but couldnt work
    What do you mean when you say it couldn't work?


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    Re: Netlist is different between schematic and layout

    Quote Originally Posted by Junus2012
    Through your explanation, I now understand that this kind of resistor can not work with equal voltages at the terminals
    Such conclusion is too strong and is wrong in general. The devil is in details, as usual.
    As long as distributed admittances around the structure can be considered as negligible, it might work properly.
    Such conditions might be meet, in case when such mosfets are minimum width, with small area, makes diode very low leaky (in number relative to drain-source leakage) and with strict operation conditions (strict DC level and small range of temperature - in bio-med applications, no one consider 125C of operating temperature).
    Simply, try to repeat simulations but not around half rail 1.65V but around 0 (simply remove 1.65 from your dc sources). The most probably, diodes will not be triggered or the effect be much smaller.

    Quote Originally Posted by Junus2012
    however, still one question in my mind which you forgot to answer me, what is the thing that made it work perfectly when I connect the bulk to the VDD rather than to the source.
    This question is already answered.
    By tying bulk to VDD, you connecting well to VDD, so mentioned diodes are no longer tying down VOC terminal to ground.

    About attached circuits.
    In bio-medical applications, where band in range of 10mHz to 10kHz is needed, people looking for extraordinary implementation of very high resistance to achieve sub-Hz cut-off frequency of filter.
    In the first figure, the bulk connection is not shown, so you cannot say that bulk is connected to source (maybe authors mentioned it in paper, I don't know). Also, VOUT+/- terminals are usually not equal.

    In configuration in both 2nd and 3rd figures we don't know whether supply is unipolar or bipolar. If it is unipolar and baseline is set to ground, even for bulk shorted to source, problem which you found in simulations doesn't apply - the voltage drop on diode is 0. So, there is no current tying down middle point of pseudoresistor. Also, in Fig. 2 opamp take care on any potential leakage current flowing through the diode. Finally, as I mentioned at the beginning, there might be a few unspoken assumptions allowing circuit to work.


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    Re: Netlist is different between schematic and layout

    Dear Suta,

    Thank you for your reply, I ment I tried your suggestion but doesnt fix the problem

    Dear Dominik,

    Thank you once again for your useful explanation, I have removed the 1.65 source and re-simulated the circuit from zeo as you suggested, below are the new simulation setup with the new result, to be considered further with you

    Click image for larger version. 

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    Thank you

    - - - Updated - - -

    Here I repeated the design of the same circuit but by using minimum channel width and length (W= 0.4 m , L = 0.4 m), results seems even worse

    Click image for larger version. 

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    - - - Updated - - -

    An extended question please Dominik,

    You said that Vout+ and Vout- are not always the same, but ideally under steady state operation Vout+ =Vout-= VCM, if there is a difference I think it mens it is an offset, which should be in order of maximum several milivolts in case of bad design, isnt it ?



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    Re: Netlist is different between schematic and layout

    Quote Originally Posted by Junus2012 View Post
    Dear Suta,

    Thank you for your reply, I ment I tried your suggestion but doesnt fix the problem
    My suggestion was not meant to fix the problem, it was meant to show/explain the problem. You said you saw the problem in extracted netlist but not in schematic. So, I suggested to add those diodes in the schematic and see if you get the same or similar behavior as in the extracted simulation.


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    Re: Netlist is different between schematic and layout

    Quote Originally Posted by sutapanaki View Post
    My suggestion was not meant to fix the problem, it was meant to show/explain the problem. You said you saw the problem in extracted netlist but not in schematic. So, I suggested to add those diodes in the schematic and see if you get the same or similar behavior as in the extracted simulation.
    Thank you Suta,
    your suggestion was useful to simulate the error, as also investigated by Dominik, therefore I updated my simulation to look for your further comments

    thank you again



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