+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Newbie level 2
    Points: 1,249, Level: 7

    Join Date
    Jul 2013
    Posts
    4
    Helped
    0 / 0
    Points
    1,249
    Level
    7

    14 bit adc output to 5 bit data conversion in VHDL

    I am having 14 bit ADC data which is in 2's complement format.
    I require to convert in 5 bit format using vhdl language. What is the easiest way of doing it apart from using if then else statements comparing magnitude?
    Consider the input data to be in two cases unsigned and signed.

    •   AltAdvertisement

        
       

  2. #2
    Full Member level 3
    Points: 1,374, Level: 8

    Join Date
    Apr 2017
    Posts
    174
    Helped
    35 / 35
    Points
    1,374
    Level
    8

    Re: 14 bit adc output to 5 bit data conversion in VHDL

    Try using resize from numeric_std on signed data type.
    https://www.csee.umbc.edu/portal/hel...meric_std.vhdl



    •   AltAdvertisement

        
       

  3. #3
    Super Moderator
    Points: 82,155, Level: 69
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    16,671
    Helped
    3779 / 3779
    Points
    82,155
    Level
    69

    Re: 14 bit adc output to 5 bit data conversion in VHDL

    Hi,

    Maybe I misunderstand..

    But if you want to generate 5 (linear. Not logarithmic like u-law, A-law) bits from a 14 bit ADC ... then just use the 5 upper bits and ignore the 9 lower significant bits.

    Klaus
    Please dont contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



    •   AltAdvertisement

        
       

  4. #4
    Super Moderator
    Points: 265,480, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    46,385
    Helped
    14117 / 14117
    Points
    265,480
    Level
    100

    Re: 14 bit adc output to 5 bit data conversion in VHDL

    But if you want to generate 5 (linear. Not logarithmic like u-law, A-law) bits from a 14 bit ADC ... then just use the 5 upper bits and ignore the 9 lower significant bits.
    May be the question is that trivial, may be some specific coding is intended. The OP missed to ask a clear question.



--[[ ]]--