Changing frequency of input clock port

Hi.

I'm using ultrasclae+ . I want to use the xapp1315 in my design for 1:7 deserialization.

In Xapp1315 design file, an external clock is used to enter the fpga through IBUFGDS.



But in my design, there are many other logics, so xapp1315 design can not be top file.

The main problem is that I have only 50MHz external input clock port, but this xapp 1315 design doesn't support this frequency.

The solution I thought was as follows.




Since the input of IDELAYE3 was no longer coming from the IO buffer, I used a DATAIN port instead of the IDATAIN port.

(I also changed the delay_src from IDATAIN to DATAIN).



However , the simulation results are different from the original xapp1315 design.

The rx_ready signal is not asserted. The output seems as if it continues to bitslip.

Is the way I thought it was wrong?

Is it a problem to create a differential clock in mmcm or is it a problem or is IDELAYE3 misused?



Thank you for reading me the long question.

Hi. I', using xilinx Ultrascale+ FPGA
I am referring to application notes provided by xilinx.

I am going to use the reference code provided in xapp1315.

In this reference code, an external clock of 100 MHz enters to FPGA, passes IBUFDS_DIFF_OUT, and then goes to idelaye3.


I am going to design my top file containing this logic as shown in the picture below

The reference code should receive 100 MHZ external clocks (go to IBUFDS), but my top design has only 50 MHZ external clocks.


What's the best way to solve a case like this?