# Phase detector with synchronous logic (FPGA)

1. ## Phase detector with synchronous logic (FPGA)

I need to measure the relative phase of two sinusoids (around 2-2.2MHz. Both signal are always of identical frequency) using an FPGA. Both signals are sampled with an ADC at 40Msps. Everything about those two signals is synchronous to that sampling clock. Getting a phase measurement which is both accurate (like <5 degrees) and also gives unique results for a full 360 range is proving difficult.

First attempt was implementing a type 3 PD using a JK flip flop (fed by the sign bits of the ADC data). But apparently my limited sampling frequency makes the result pretty noisy, unless I average for a very long time (not acceptable).

Another option is to multiply the two signals together (type 1 PD), which should give much better precision since I'm using all the data the ADC has to offer. The issue with that is it's output is a cosine function, so it's only injective across a 180 degree range (10 and 350 degrees give the same result). And sensitivity is poor near 0 and 180.

Combining both methods together is an option, but I would still get noisy results near 0 and 180 degrees.

I can't add extra hardware at the moment. Using a fixed delay create an approximate 90 degree phase shifted version is an option, but since the frequency is not fixed, simply guessing how much delay to use to get 90 degrees would probably create significant error...

Any tips would be appreciated.

2. ## Re: Phase detector with synchronous logic (FPGA)

Can you just get the two positive-going zero crossings
and run a timer, and then do the arithmetic? Seems like
a 800MHz clock would get you better than 1 degree
resolution. Accuracy might have to do with other things
like zero-crossing-compare jitter / offsets as well.

3. ## Re: Phase detector with synchronous logic (FPGA)

Hi,

DFT or correlation comes into my mind.
Not that difficult math..but good precision, even for noisy signals.

Klaus

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4. ## Re: Phase detector with synchronous logic (FPGA)

Originally Posted by dick_freebird
Can you just get the two positive-going zero crossings
and run a timer, and then do the arithmetic? Seems like
a 800MHz clock would get you better than 1 degree
resolution. Accuracy might have to do with other things
like zero-crossing-compare jitter / offsets as well.
That's basically what my first PD design was. Sure 800MHz would be great, but my sampling frequency is 40MHz (limited by the ADC).

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Originally Posted by KlausST
Hi,

DFT or correlation comes into my mind.
Not that difficult math..but good precision, even for noisy signals.

Klaus
I've never looked at implementing DFT in an FPGA before... it's not a super powerful FPGA (MAX10), so not sure if I have the resources. Could you link me a simple design example (like a block diagram)?

5. ## Re: Phase detector with synchronous logic (FPGA)

The multiply idea sketched in post #1 is basically good, but it should be extended to I/Q demodulation to work over 0 to 360 degree. You can either generate a 90° delayed copy of one input signal, exact phase shift can be adjusted by a DLL. Or lock an all-digital PLL to one signal.

Both design variants should fit a smaller MAX10. Consider that the PLL variant doesn't work well in compact flash MAX10 because it doesn't support sine tables.

6. ## Re: Phase detector with synchronous logic (FPGA)

An all digital DLL is a good idea, but I don't think it would work in this case because both signals are pulsed very briefly, about 50us. I don't think that will be long enough for a DLL to converge.

I know that 50us worth of raw sampled data is sufficient to derive a good measurement. But I think it would processing the entire dataset, rather than a simple "on the go" method like a phase detector. More suited to a microprocessor than an FPGA...

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7. ## Re: Phase detector with synchronous logic (FPGA)

The 50 us limitation wasn't mentioned yet. In this case, "processing the entire dataset" is in fact more promising. Question is if you know the exact frequency beforehand or need to extract it from the acquired waveform. Also what's the signal duty cycle? Do you have time for multiple processing passes over the stored data?

8. ## Re: Phase detector with synchronous logic (FPGA)

Exact frequency is not known beforehand, so it would have to do some sort of peak search. The duty cycle of the pulse is quite low (maybe 1ms between pulses) which helps. Still seems more amenable to a microprocessor than an FPGA, especially if the process has to be iterative.

You commented that the MAX10 flash doesn't support sine tables, could you elaborate a bit? I thought flash could be programmed arbitrarily. Or maybe it can't be accessed by the FPGA fabric?

9. ## Re: Phase detector with synchronous logic (FPGA)

A possible solution could be to determine the analysis frequency based on the zero crossings and then multiply the acquired signal with sine and cosine reference functions of this frequency.

MAX10 comes in different flavors SC, SA, DC, DF and DA. The "compact" types SC and DC have smaller built in flash and don't support ROM tables (initialized RAM). It's still possible to generate sine in combinational logic, but that's rather ineffective and only suitable for very small tables. For the intended relative coarse resolution of 5 degree it might work.

10. ## Re: Phase detector with synchronous logic (FPGA)

I'm familiar with doing phase detection in FPGA's (DFT or 'sin correlation') as suggested. The math is easy (multiply and accumulate versus sin and cos, do some algebra with the accumulator results).

However given your unknown frequency and duty cycle variation this does seem like a processor may be better. FPGA's work very well on continuous streams of data, harder when other variables and states start entering the equation.

A final idea would be to do linear interpolation of the data-points around the zero crossing to improve timing resolution and noise immunity to an extent.

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11. ## Re: Phase detector with synchronous logic (FPGA)

However given your unknown frequency and duty cycle variation this does seem like a processor may be better. FPGA's work very well on continuous streams of data, harder when other variables and states start entering the equation.
I agree that processor is simpler. Additional logic (e.g. FPGA) is however needed due to the high sample rate, unless you have a fast signal processor that can stream in samples at 40 MHz. In this situation it's always an option to perform all sequential processing in FPGA, particularly if no suitable processor is present in the sub system or you can't provide an interface with sufficient throughput.

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12. ## Re: Phase detector with synchronous logic (FPGA)

2MHz frequency on 40Msps means you have 20 samples per cycle. Thus maximum phase resolution possible is 360/20 per sample. So to get 5 degrees you need to upsample or design fractiona delay. I suggest Farrow filter and a feedback loop based on phase error detector using the two peaks then find out how much delay is there when loop converges

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13. ## Re: Phase detector with synchronous logic (FPGA)

Originally Posted by FvM
I agree that processor is simpler. Additional logic (e.g. FPGA) is however needed due to the high sample rate, unless you have a fast signal processor that can stream in samples at 40 MHz. In this situation it's always an option to perform all sequential processing in FPGA, particularly if no suitable processor is present in the sub system or you can't provide an interface with sufficient throughput.
Actually I notice now that quartus is showing an FFT block in its IP library. Not sure if I'll be able to use it for a final design (probably an evaluation version only), but at least I can test what my resource utilization will be like on my max10, if I go that route.

Originally Posted by asdf44
A final idea would be to do linear interpolation of the data-points around the zero crossing to improve timing resolution and noise immunity to an extent.
Originally Posted by kaz1
2MHz frequency on 40Msps means you have 20 samples per cycle. Thus maximum phase resolution possible is 360/20 per sample. So to get 5 degrees you need to upsample or design fractiona delay. I suggest Farrow filter and a feedback loop based on phase error detector using the two peaks then find out how much delay is there when loop converges
Never seen farrow filters before, sounds pretty neat. I definitely don't have enough DSP resources for a bunch of FIR filters though.

Simply interpolating my 40MHz data never occurred to me. Perhaps upsampling to 80MHz (160MHz would be really pushing it) and feeding that to my type III PD might be good enough for now...

14. ## Re: Phase detector with synchronous logic (FPGA)

2MHz frequency on 40Msps means you have 20 samples per cycle. Thus maximum phase resolution possible is 360/20 per sample.
I don't agree. You get a much higher phase resolution by I/Q demodulation, only limited by the ADC resolution and signal noise.

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