+ Post New Thread
Results 1 to 7 of 7
  1. #1
    Full Member level 2
    Points: 2,892, Level: 12

    Join Date
    Jan 2007
    Posts
    121
    Helped
    0 / 0
    Points
    2,892
    Level
    12

    Switch size in a resistive trim network ?

    The picture shows resistive trim networks.
    I am using a 0.18um CMOS process.
    How should I choose the NMOS switch size (W/L) for the resistive network 1 and 2 ?
    What criteria decides the required ON resistance for the NMOS switches ?

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 3
    Points: 5,246, Level: 17

    Join Date
    Nov 2013
    Posts
    767
    Helped
    214 / 214
    Points
    5,246
    Level
    17

    Re: Switch size in a resistive trim network ?

    Use minimum L, and choose the minimal W with the following conditions:
    - lowest gate voltage applied
    - slow-slow (SS) process
    - cold temperature (but maybe the hottest temp is also recommended to try)
    - select only the top device, switch off the lower ones
    - set Ron at least 10 times samller than R

    Use the same width for all switching devices is recommended.
    You can do it with both branch, network.
    If the sizes are too big you should increase the value of R or you can set a bit smaller width for the lower switches, or lower finger number, multiplication factor.
    "Try SCE to AUX." /John Aaron/



  3. #3
    Advanced Member level 5
    Points: 41,023, Level: 49

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,607
    Helped
    1949 / 1949
    Points
    41,023
    Level
    49

    Re: Switch size in a resistive trim network ?

    I recommend considering the resistor segment and the switch
    as the resistor-bank "unit cell", and repeating this as you make
    series / parallel arrangements.

    Switch Ron vs common mode is a secondary concern which
    might make you favor parallel links with the NMOS switches
    all at vssa! potential.

    Depending on sensitivities you might want to use greater
    than minimum L especially on links which could see near
    full rail voltage, to ensure that leakage remains negligible
    at fast*hot. I would not count on models showing you
    the range of leakage-floor and subthreshold leakage that
    production material eventually will.



    •   AltAdvertisement

        
       

  4. #4
    Full Member level 2
    Points: 2,892, Level: 12

    Join Date
    Jan 2007
    Posts
    121
    Helped
    0 / 0
    Points
    2,892
    Level
    12

    Re: Switch size in a resistive trim network ?

    In your reply you said " select only the top device, switch off the lower ones". Does it mean turn ON the topmost NMOS switch M1 and turn OFF all the switches below it ?

    Also "set Ron at least 10 times smaller than R" . For the trim network 2 in the picture, should I place the lowest resistance R in the topmost position initially and then perform the above test ?

    Please clarify.



  5. #5
    Advanced Member level 3
    Points: 5,246, Level: 17

    Join Date
    Nov 2013
    Posts
    767
    Helped
    214 / 214
    Points
    5,246
    Level
    17

    Re: Switch size in a resistive trim network ?

    Yes, it means. Also, no, don't place R to the top. It is more effective if you can shunt R (the samllest resistance unit value) with the lowest NMOS. The lowest NMOS can produce the lowest Ron to shunt R effectively.
    "Try SCE to AUX." /John Aaron/



    •   AltAdvertisement

        
       

  6. #6
    Full Member level 4
    Points: 1,518, Level: 8

    Join Date
    Jul 2016
    Posts
    195
    Helped
    2 / 2
    Points
    1,518
    Level
    8

    Re: Switch size in a resistive trim network ?

    Can I hack this thread and take the opportunity to ask the following:

    What would be your considerations for pull-down and pull-up transistors to urn of bits of circuits? Like current DACs, current sources, amplifiers, etc? What size would you consider for this? Its 130nm process in this case.

    Another question would've, for current DACs where.yiu have to put switch's in series with the mirror, what would be your considerations for their sizing? My first guess is related to the currents that are passing through them but not sure and not sure what additional considerations would have to be taken into account.

    Thanks in advance.



  7. #7
    Advanced Member level 3
    Points: 5,246, Level: 17

    Join Date
    Nov 2013
    Posts
    767
    Helped
    214 / 214
    Points
    5,246
    Level
    17

    Re: Switch size in a resistive trim network ?

    Gate pull-up/down is done by devices with minimal length and relatively small width, not wider than 1um. To make it stronger and more confident the multiplier of the devices can be increased, but one device should be enough to sink any reference current, if it is not possible to switch that current off.

    For current DACs it can help if the size of the switch is matched to the source or to the cascode device, normally small even multiplier is enough, it will have layout benefits. Keep the Vds of the switch device under its saturation voltage in the worst case corner then it will be fine and won't cause headroom issues, and use smallest length. The last is totally related to applied current you have just mentioned, shouldn't be hard to fulfill, and another consideration is that you probably use a digital cell to drive the switch which should be comparable in size with the switch to eliminate big delays. If it isn't, use chain of increaseing buffers,inverters to force drive capability for the switches.
    "Try SCE to AUX." /John Aaron/



--[[ ]]--