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  1. #1
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    Design CMOS transmission gate for digital switch in programmable resistors

    Dear friends,

    I see most of the designers makes the PMOS transistor three times bigger than NMOS (to compensate for mobility difference) when designing the TG, what this lead in actual circuit performance, while Ron(tG) = RN||RP, it means if the target to reduce RON then we can make NMOS=PMOS and increase them both, what is the advantagues of having ratio in between ?


    For my application, I using the TG to selectviliely making shorts on some of resistors (by connecting it in parallel to the resistor, so when it is on it will shot this unit) to have programmable resistors , does really the symetry of the TG will be matter ?

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  2. #2
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    Re: Design CMOS transmission gate for digital switch in programmable resistors

    There are three regions..
    1. Only pMOS is on.
    2. Only nMOS is on
    3. Somehwere in between
    You would want the same resistance in all the three regions to avoid distortion. To satisfy the same resistance between 1 and 2, we use the different sizes. And then we pray we get the same in between. Does not happen sub 100nm nodes.



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