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  1. #1
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    parasitic cell blocking

    Hi ,

    At the moment I am trying to perform parasitic extraction using PVS-Quantus to get the RLC parasitics of the metal stack (routing).
    the Pcell of my the transistor already includes RLC parasitics , I want this part of the layout to be blocked from parasitic extraction to avoid parasitics double counting

    To do that :
    • I preserved the Pcell during PVS LVS using preserve_cell_list in PVL.
    • Then I introduced the cell to be blocked which is the Pcell to PVS Quantus tool in a txt file as pcellname_CDNS* .

    checking fT and fmax of the transitor I can see that there is parasitics double counting (10-15% degradation).

    any idea how solve this issue ?

    Br.

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  2. #2
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    Re: parasitic cell blocking

    Have you changed the corner after extraction for simulation? Typically schematic simulations and extracted simulations are done with different corners.



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  3. #3
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    Re: parasitic cell blocking

    Quote Originally Posted by vivekroy View Post
    Have you changed the corner after extraction for simulation? Typically schematic simulations and extracted simulations are done with different corners.
    I am using nominal (typical) corner for both schematic and extraction.



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  4. #4
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    Re: parasitic cell blocking

    There is something called a "pre" sim and "post" sim.. Check your PDK documents.

    Which technology is this?



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