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    how to generate 4MHz clock from 2 MHz clock.

    Hi,

    I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.

    I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.

    can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??

    what are the other methods to do that??

    Regards
    Ankit

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    Re: how to generate 4MHz clock from 2 MHz clock.

    This cheap IC does perfect job for your purpose:
    https://www.maximintegrated.com/en/d...es/3/3327.html


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    Re: how to generate 4MHz clock from 2 MHz clock.

    If you have a higher frequency clock available, a digital PLL can generate the 4 MHz clock, however limited to the time resolution of the system clock. Ultimately, you can phase lock an auxiliary high frequency clock to the 2 MHz input, using MMCM dynamic phase shift feature and some user logic.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Hi,

    Which FPGA are you talking about?

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by KlausST View Post
    Hi,

    Which FPGA are you talking about?

    Klaus
    Must be a Xilinx part (MMCM/PLL), but can't tell which one as more than one of the families has that primitive. Though it can be narrowed down with the OP's statement that the wizard says the FPGA can only support a lower frequency of 10 MHz for the PLL input clock.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    10 MHz minimal clock input frequency is common series 7 MMCM spec as far as I'm aware of.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    The OP has posted the same Q in Xilinx forums yesterday and did not provide sufficient details in order to answer his Q.
    My answer to him would be the same here as there.

    The PLL/MMCM inside the Arty board is capable of min 10Mz o/p or more. ads-ee/FvM have also pointed that out.
    This was the reason why it was asked to him the source of this 2MHz clk and to it there has been no info from the OP.

    Dear OP, no matter in forum you go, if you are not providing sufficient details, you won't get proper answers.
    Last edited by dpaul; 14th February 2020 at 09:32.
    FPGA enthusiast!


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    Re: how to generate 4MHz clock from 2 MHz clock.

    Possible solutions have been sketched, but the application requirements are yet unknown.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by dpaul View Post

    The PLL/MMCM inside the Arty board is capable of min 10Mz o/p or more. ads-ee/FvM have also pointed that out.
    This was the reason why it was asked to him the source of this 2MHz clk and to it there has been no info from the OP.
    The 2 Mhz clock is generated from the input data using the clock recovery algorithm. I require one 4 MHZ clock that must be synchronize to this 2 MHz clock. If i use arty board clock to generate 4 MHz than both clock would not be synchronize. and i don't know how to synchronize/align two clocks generated from different sources.

    So I thought it would be better if I can generate 4 MHz clock from my original 2 MHZ clock .

    - - - Updated - - -

    Quote Originally Posted by FvM View Post
    If you have a higher frequency clock available, a digital PLL can generate the 4 MHz clock, however limited to the time resolution of the system clock. Ultimately, you can phase lock an auxiliary high frequency clock to the 2 MHz input, using MMCM dynamic phase shift feature and some user logic.

    So if i understand correctly, you want to say that i have 2 MHz clock , I should generate 4 MHz clock from clocking wizard/PLL/MMCM and than synchronize them using MMCM dynamic phase shift feature.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Arty board
    FPGA part : XC7A35TICSG324-1L



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by ankit rajput View Post
    I require one 4 MHZ clock that must be synchronize to this 2 MHz clock.
    This simple frequency doubler turns up via internet search. XOR (exclusive-OR) gate turns on at upward and downward transitions. RC values are not critical.

    Click image for larger version. 

Name:	clk freq doubler via XOR gate RC network (2 MHz in 4 MHz out).png 
Views:	2 
Size:	19.1 KB 
ID:	157820



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    Re: how to generate 4MHz clock from 2 MHz clock.

    So if i understand correctly, you want to say that i have 2 MHz clock , I should generate 4 MHz clock from clocking wizard/PLL/MMCM and than synchronize them using MMCM dynamic phase shift feature.
    A bit more complex. You'll design a kind of software PLL with 2 and 4 MHz output, locked to the 2 MHz reference. Dynamic phase shift might be used if the phase jitter requirements are very strict. More likely you'll just oversample the 2 MHz input with a sufficient fast system clock.

    We didn't yet hear about your requirements and available clocks.

    The 2 Mhz clock is generated from the input data using the clock recovery algorithm.
    Do you mind to sketch what the input data is and how the 2 MHz clock is "recovered"?



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by FvM View Post
    Do you mind to sketch what the input data is and how the 2 MHz clock is "recovered"?
    My input is a 2 MHz data coming from another Arty FPGA board. and 2 MHz clock is recovered using the code mentioned in xilinx application note XAPP868 (https://www.xilinx.com/support/docum...es/xapp868.pdf).



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    Re: how to generate 4MHz clock from 2 MHz clock.

    The xapp868 design is a digital PLL that can easily generate 4 MHz along with the 2 MHz output.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by FvM View Post
    The xapp868 design is a digital PLL that can easily generate 4 MHz along with the 2 MHz output.
    oh.. I didn't knew that. Let me check how to generate 4 MHz along with 2 MHz clock.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    See how 2 MHz clock is derived from DDS MSB phase[31]. You can generate 4 MHz in a similar way by utilizing phase[30] too.


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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by FvM View Post
    See how 2 MHz clock is derived from DDS MSB phase[31]. You can generate 4 MHz in a similar way by utilizing phase[30] too.
    I tried to do that. The VCO file(voltage controlled oscillator) is in .ngc format. So , I cannot open it. But even i tried to take phase [14] (because in verilog example phase width is 16 instead of 32) . But phase [14] or phase [15] is not at all related to 2 MHz or 4 MHz clock output. what is the correct way to take 4 MHz output?



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    Re: how to generate 4MHz clock from 2 MHz clock.

    I was referring to xapp868 where a 32 bit DDS is running at 2.048 MHz. Not sure how your design is different. What's the DDS phase accumulator frequency in your design?



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by FvM View Post
    I was referring to xapp868 where a 32 bit DDS is running at 2.048 MHz. Not sure how your design is different. What's the DDS phase accumulator frequency in your design?
    i am using the same xapp868 design for clock recovery. I was saying that in the verilog code of this xapp868, phase width of 16 has been taken instead of 32.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    I was taking this as granted. But what's the DDS frequency if it's not 2 MHz? Does your design involve an additional frequency divider between the DDS and the phase-frequency detector?



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