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Open Collector design Question

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theboss4

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I'm trying to design a open collector circuit that will tolerate 7v across the transistor. The issue i'm having is that the transistor devices in my design kits can only support voltage no larger than 4.5v. Can you suggest anything that I could do to make the circuit more robust?

Please let me know.

Thanks in advance. Capture2.JPGCapture.JPG
 

You might be able to make a cascode open-drain stage
if you have a HV well or a SOI tub to put the guard NMOS
into. Tie its gate to VDD, source to the "master" switch
NMOS below, drain is the "open collector" output.

But plain cheap JI technology would still leave you with
Vdb=7V and this isn't going to fly, most likely. There's
also the challenge of ESD protection of a pin that's
supposed to not break down below 7V.

Many CMOS flows will let you make (whether or not
the rules allow) LDMOS devices. Like "good ol' C5"
has, I think, 12V-ish LDMOS devices either in the
main flow or as a few-mask "module", TowerJazz
CA18 has 12, 20 and 40V LDMOS in its 1.8/3.3
and 1.8/5V flows, etc.
 

Thanks for the feedback "dick_freebird". Unfortunately, I have to use this process (SiGe), not an SOI or LDMOS process, therefore I can't take advantage of any of the High voltage device or techniques you mentioned.

I was trying to add several diode drop NPNs before the main device, but it pull up the 0v to a higher volt when the switch is in the "ON" position.

Please let me know if you (or anyone else) have additional suggestions.

Thanks!
 

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