Problems about DFT and ADC in Impedance Converter

Hi everyone, I am studying to use FPGA to do impedance measure. Therefore, I refer to AD5933 Impedance Converter to study their structures and implement it in FPGA.

There are several things not clear when I studying the datasheet. Since I cannot find out any solution of my questions from the datasheet, hopefully, can get some help here. Maybe I have some conceptional misunderstanding in data processing, please correct me if I am wrong.

Here is the diagram of ad5933



Q1. Is the DAC and ADC are in different sampling rates? Since I saw the ADC is 1MSPS but cannot find the sampling rate for DAC

Q2. Is the sampling rate of ADC is constantly 1MSPS?? Would it be changed internally depends on the input signal`s frequency??

Q3. If the ADC has a constant sample rate at 1MSPS,

Let say, dds output 10kHz sinewave then it would have 100 samples per 1 sinewave cycle. Total 10.24 cycles would pass to the 1024 DFT to process.

But, when dds output 10Hz sinewave, now has 100k samples per cycle1 sinewave cycle. A 1024 DFT can only fit 1% samples from the entire samples. How would it be possible??

My main problems is Q3. Since I have to design a buffer to collect at least one period of the signal(10Hz to 10kHz). If the ADC sampling rate is too high. The buffer and DFT size would be unrealistically large. Is there anything I missed?


Thanks for any help on this.

Consider that the datasheet system diagram is simplified. As you already found out, it's no possible to cover the supported frequency range with fixed ADC sampling rate and 2048 samples window length. Instead of guessing about the missing info in datasheet, I would refer to DSP literature and known methods for performing phase selective signal processing, e.g. Goertzel algorithm.

I would expect constant DAC and ADC sample rate (100 kSPS/1MSPS) and some kind of decimation between ADC and DFT.