Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Phase shift full bridge controller datasheet gives misleading info?

Status
Not open for further replies.
T

treez

Guest
Page 1 of the UCC28951 datasheet states………………..

“Programmable delays ensure ZVS operation over a wide range of operating conditions, while the load current naturally tunes the switching delays of the secondary-side synchronous rectifiers(SR). This functionality maximizes overall system efficiency.”
If also states that “light load efficiency management is possible with programmable adaptive delays”

UCC28951 datasheet:
https://www.ti.com/lit/ds/symlink/ucc28951.pdf

..However, this is misleading, it is not adaptive delays that help to bring about ZVS….rather, it is the sizing of the primary side series inductor…this is confirmed by the following document…
Simplified Phase-Shifted Full-Bridge Converter Design

**broken link removed**
…..where it says…
“There are many pulse-width modulators (PWM) on the market for controlling a phase-shifted, full-bridge converter with programmable adaptive delays, including Texas Instruments’ new UCC28950 phase-shifted, full-bridge controller. These adaptive delays are used by some engineers to try to reduce the body diode conduction of the H-bridge FETs, which is not the easiest of things to achieve, and also may be difficult to maintain in mass production. The adaptive delay approach used to reduce body diode conduction losses have led to the misconception that adaptive delays are required to achieve zero voltage switching in a phase-shifted, full-bridge converter. Since the average capacitance at the switch nodes (QBd and QDd) and LS and LLK remain approximately the same over line and load, the resonant tank frequency of the switch nodes (fR) should remain roughly the same. Since fR remains roughly the same with the proper selection of LS and LLK, Zero voltage switching can be achieved from 50 to 100 percent load with fixed turn on delays (tAB_DELAY, tCD_DELAY) for FETs QA through QD.”

Would you agree that the UCC28951 datasheet is misleading here?
 

Adaptive delays help you balance ZVS operation with dead time diode conduction losses.

On a super quick look they tie the ADEL (adaptive delay) pin to the current sense so dead time can change with current. That makes sense since low currents mean slower commutation and mean you need more dead time for ZVS operation. But you don't want long dead times all the time because it means diode conduction losses at higher currents.


I've seen chips with an alternative scheme of sensing the switch node voltage and 'seeing' when it has commutated.
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
the dead time of the so called passive leg of the H bridge needs extending at light load as there is insufficient energy/current for the voltage to completely swing to the other rail in a short time - so a longer time is needed for it to get close to the other - hence adaptive dead time.

We have used additional commutation chokes in our larger converters to ensure the passive ( or lagging leg ) side always has plenty of current at turn off - so the dead time can be fixed and ZVS is achieved over the full load range

I have not considered the effects w.r.t sec side fet operation ...
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Additional parallel or series inductance? Only parallel inductance could ensure ZVS at very light or no load (while adding circulating current losses).

Gan or SiC is helpful to deal the light load hard switching in this topology and widen the range of ZVS operation due to lower C.



I answered hastily above before seeing your post already cited diode losses: Simply put if you don't have adaptive control you'll probably choose a dead time that's lower than if you do, clamping off some possible ZVS operation.
 

Additional parallel or series inductance?
neither, from the mid point of the leading leg to a fixed V point.

I think the term leading leg refers to the leg that turns on to initiate a power pulse thru the Tx, this is the one starved of current at light load - the lagging leg is the one to turn off at the end of a power pulse and therefore always has some current ( except at close to zero phase shift ) ...
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Another point of contention in the UCC28950 datasheet is on page 61...

Page 61 of the UCC28950 PSFB (with sync rects) controller datasheet states that an RCD clamp is needed across the sync rect FETs to “avoid overvoltage due to switch node ringing”.
…But surely the RCD clamp in such a case is there to stop overvoltages which come about due to brief reversals of the secondary inductor current when the sync FET turns OFF whilst flowing reversing inductor current….the RCD clamp prevents overvoltages from that incidence.
Surely the switch node overvoltage ringing would be there even if the sync fet was not there (ie just a diode there)…and this ringing would be addressed with RC snubbering, not an RCD clamp?

UCC28950 Datasheet
https://www.ti.com/lit/ds/symlink/ucc28950.pdf
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top