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Quartus error 12006 'undefined entity'

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barry

barry

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I'm using Quartus Prime Lite and generated a clock buffer IP (using ALTIOBUF). It synthesizes fine in Synplify Pro, but when I try to compile the netlist, Quartus gives the error: "Error (12006): Node instance "clk_buf_altclkctrl_0_sub_component" instantiates undefined entity "clk_buf_altclkctrl_0_sub_0". I've included the file clk_buf.qip in the Quartus project.

My IP is instantiated here:

Code: 
//clock buffers
	clk_buf CK_MAIN (
		.inclk  (clk_in),  
		.outclk (clk)  
	);

	clk_buf CK_SPI (
		.inclk  (spi_clk_in),  
		.outclk (spi_clk)  
	);

What's going on? Do I need to include some other file in Quartus? I've got RAM IP instantiated, and that worked fine,with no extra massaging required, but when I added the clock buffer, everything blew up.
 

What device are you using?
Are both clock buffer outputs connected to physical pins on the device?
 

It's a spartan 4. The buffer outputs go to the fabric, the inputs go to top level ports.
 

I wonder what's the purpose of the clock buffers in your design? Normally, Quartus is infering buffers autimatically, you don't need to think about it.
 
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    barry

    barry

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FvM said:
I wonder what's the purpose of the clock buffers in your design? Normally, Quartus is infering buffers autimatically, you don't need to think about it.
Click to expand...

Aha! Thanks.

I'm a Xilinx guy. I searched a lot for any mention in the Intel docs, but didn't find much about clock buffers, but they did let me create one anyway. My whole problem stemmed from not meeting timing, so I thought I might need a clock buffer. But the actual problem was that Quartus did not import my constraints like I though it should, then, for some reason, set the default clock constraint to 1GHz then told me I didn't meet timing.
 

Spartan 4 is a Xilinx device. Quartus is an Altera tool.
 

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