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  1. #1
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    How to create an IP core based on a project in ISE?

    Greetings ... a couple of days ago I have been doing a project in ISE 14.5 and for this I need to create an IP that is based on a small project (programmable clock) that I have also implemented in ISE 14.5. I would like to know if it is possible to package the small project in an IP?
    I leave attached the source code of the top file.
    Code:
    `timescale 1ps/1ps
    
    module top_mmcme2
       (
          // SSTEP is the input to start a reconfiguration.  It should only be
          // pulsed for one clock cycle.
          input    SSTEP,
          // STATE determines which state the MMCM_ADV will be reconfigured to.  A
          // value of 0 correlates to state 1, and a value of 1 correlates to state
          // 2.
          input    STATE,
    
          // RST will reset the entire reference design including the MMCM_ADV
          input    RST,
          // CLKIN is the input clock that feeds the MMCM_ADV CLKIN as well as the
          // clock for the MMCM_DRP module
          input    CLKIN,
    
          // SRDY pulses for one clock cycle after the MMCM_ADV is locked and the
          // MMCM_DRP module is ready to start another re-configuration
          output   SRDY,
          output   LOCKED,
    
          // These are the clock outputs from the MMCM_ADV.
          output   CLK0OUT,
          output   CLK1OUT,
          output   CLK2OUT,
          output   CLK3OUT,
          output   CLK4OUT,
          output   CLK5OUT,
          output   CLK6OUT,
          input [15:0] i_mmcm_ctrl
       );
    
       // These signals are used as direct connections between the MMCM_ADV and the
       // MMCM_DRP.
       (* mark_debug = "true" *) wire [15:0]    di;
       (* mark_debug = "true" *) wire [6:0]     daddr;
       (* mark_debug = "true" *) wire [15:0]    dout;
       (* mark_debug = "true" *) wire           den;
       (* mark_debug = "true" *) wire           dwe;
       wire           dclk;
       wire           rst_mmcm;
       wire           drdy;
    	reg				current_state;
    	reg [7:0]		sstep_int ;
    	reg				init_drp_state = 1;
    
       // These signals are used for the BUFG's necessary for the design.
       wire           clkin_bufgout;
    
       wire           clkfb_bufgout;
       wire           clkfb_bufgin;
    
       wire           clk0_bufgin;
    
       wire           clk1_bufgin;
    
       wire           clk2_bufgin;
    
       wire           clk3_bufgin;
    
       wire           clk4_bufgin;
    
       wire           clk5_bufgin;
    
       wire           clk6_bufgin;
       
       assign CLKIN_ibuf = CLKIN;
       BUFG BUFG_IN (
          .O(clkin_bufgout),
          .I(CLKIN_ibuf)
       );
    
       BUFG BUFG_FB (
          .O(clkfb_bufgout),
          .I(clkfb_bufgin)
       );
    
       BUFG BUFG_CLK0 (
          .O(CLK0OUT),
          .I(clk0_bufgin)
       );
    
       BUFG BUFG_CLK1 (
          .O(CLK1OUT),
          .I(clk1_bufgin)
       );
    
       BUFG BUFG_CLK2 (
          .O(CLK2OUT),
          .I(clk2_bufgin)
       );
    
       BUFG BUFG_CLK3 (
          .O(CLK3OUT),
          .I(clk3_bufgin)
       );
    
       BUFG BUFG_CLK4 (
          .O(CLK4OUT),
          .I(clk4_bufgin)
       );
    
       BUFG BUFG_CLK5 (
          .O(CLK5OUT),
          .I(clk5_bufgin)
       );
    
       BUFG BUFG_CLK6 (
          .O(CLK6OUT),
          .I(clk6_bufgin)
       );
    
       // MMCM_ADV that reconfiguration will take place on
       MMCME2_ADV #(
          // "HIGH", "LOW" or "OPTIMIZED"
          .BANDWIDTH("OPTIMIZED"),
          .DIVCLK_DIVIDE(1), // (1 to 106)
    
          .CLKFBOUT_MULT_F(6), // (2 to 64)
          .CLKFBOUT_PHASE(0.0),
          .CLKFBOUT_USE_FINE_PS("FALSE"),
    
          // Set the clock period (ns) of input clocks
          .CLKIN1_PERIOD(10.000),
          .REF_JITTER1(0.010),
    
          .CLKIN2_PERIOD(10.000),
          .REF_JITTER2(0.010),
    
          // CLKOUT parameters:
          // DIVIDE: (1 to 128)
          // DUTY_CYCLE: (0.01 to 0.99) - This is dependent on the divide value.
          // PHASE: (0.0 to 360.0) - This is dependent on the divide value.
          // USE_FINE_PS: (TRUE or FALSE)
    
          .CLKOUT0_DIVIDE_F(6),
          .CLKOUT0_DUTY_CYCLE(0.5),
          .CLKOUT0_PHASE(0.0),
          .CLKOUT0_USE_FINE_PS("FALSE"),
    
          .CLKOUT1_DIVIDE(3),
          .CLKOUT1_DUTY_CYCLE(0.5),
          .CLKOUT1_PHASE(0.0),
          .CLKOUT1_USE_FINE_PS("FALSE"),
    
          .CLKOUT2_DIVIDE(24),
          .CLKOUT2_DUTY_CYCLE(0.5),
          .CLKOUT2_PHASE(0.0),
          .CLKOUT2_USE_FINE_PS("FALSE"),
    
          .CLKOUT3_DIVIDE(24),
          .CLKOUT3_DUTY_CYCLE(0.5),
          .CLKOUT3_PHASE(0.0),
          .CLKOUT3_USE_FINE_PS("FALSE"),
    
          .CLKOUT4_DIVIDE(24),
          .CLKOUT4_DUTY_CYCLE(0.5),
          .CLKOUT4_PHASE(0.0),
          .CLKOUT4_USE_FINE_PS("FALSE"),
          .CLKOUT4_CASCADE("FALSE"),
    
          .CLKOUT5_DIVIDE(24),
          .CLKOUT5_DUTY_CYCLE(0.5),
          .CLKOUT5_PHASE(0.0),
          .CLKOUT5_USE_FINE_PS("FALSE"),
    
          .CLKOUT6_DIVIDE(36),
          .CLKOUT6_DUTY_CYCLE(0.5),
          .CLKOUT6_PHASE(0.0),
          .CLKOUT6_USE_FINE_PS("FALSE"),
    
          // Misc parameters
          .COMPENSATION("ZHOLD"),
          .STARTUP_WAIT("FALSE")
       ) mmcme2_test_inst (
          .CLKFBOUT(clkfb_bufgin),
          .CLKFBOUTB(),
    
          .CLKFBSTOPPED(),
          .CLKINSTOPPED(),
    
          // Clock outputs
          .CLKOUT0(clk0_bufgin),
          .CLKOUT0B(),
          .CLKOUT1(clk1_bufgin),
          .CLKOUT1B(),
          .CLKOUT2(clk2_bufgin),
          .CLKOUT2B(),
          .CLKOUT3(clk3_bufgin),
          .CLKOUT3B(),
          .CLKOUT4(clk4_bufgin),
          .CLKOUT5(clk5_bufgin),
          .CLKOUT6(clk6_bufgin),
    
          // DRP Ports
          .DO(dout), // (16-bits)
          .DRDY(drdy),
          .DADDR(daddr), // 5 bits
          .DCLK(dclk),
          .DEN(den),
          .DI(di), // 16 bits
          .DWE(dwe),
    
          .LOCKED(LOCKED),
          .CLKFBIN(clkfb_bufgout),
    
          // Clock inputs
          .CLKIN1(CLKIN_ibuf),
          .CLKIN2(),
          .CLKINSEL(1'b1),
    
          // Fine phase shifting
          .PSDONE(),
          .PSCLK(1'b0),
          .PSEN(1'b0),
          .PSINCDEC(1'b0),
    
          .PWRDWN(1'b0),
          .RST(rst_mmcm)
       );
    
       // MMCM_DRP instance that will perform the reconfiguration operations
       mmcme2_drp #(
          //***********************************************************************
          // State 1 Parameters - These are for the first reconfiguration state.
          //***********************************************************************
          // Set the multiply to 6.0 with 0 deg phase offset, optimized bandwidth, input divide of 1
          .S1_CLKFBOUT_MULT(6),
          .S1_CLKFBOUT_PHASE(000_000),
          .S1_CLKFBOUT_FRAC(000),
          .S1_CLKFBOUT_FRAC_EN(0),
    
          .S1_BANDWIDTH("OPTIMIZED"),
          .S1_DIVCLK_DIVIDE(1),
    
          // Set clockout0 to a divide of 6.0 (unity gain), 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT0_DIVIDE(6),
          .S1_CLKOUT0_PHASE(000_000),
          .S1_CLKOUT0_DUTY(50000),
          .S1_CLKOUT0_FRAC(000),
          .S1_CLKOUT0_FRAC_EN(0),
    
          // Set clockout 1 to a divide of 1, 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT1_DIVIDE(1),
          .S1_CLKOUT1_PHASE(000_000),
          .S1_CLKOUT1_DUTY(50000),
    
          // Set clockout 2 to a divide of 2, 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT2_DIVIDE(2),
          .S1_CLKOUT2_PHASE(000_000),
          .S1_CLKOUT2_DUTY(50000),
    
          // Set clockout 3 to a divide of 3, 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT3_DIVIDE(3),
          .S1_CLKOUT3_PHASE(000_000),
          .S1_CLKOUT3_DUTY(50000),
    
          // Set clockout 4 to a divide of 4, 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT4_DIVIDE(4),
          .S1_CLKOUT4_PHASE(000_000),
          .S1_CLKOUT4_DUTY(50000),
    
          // Set clockout 5 to a divide of 5, 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT5_DIVIDE(5),
          .S1_CLKOUT5_PHASE(000_000),
          .S1_CLKOUT5_DUTY(50000),
    
          // Set clockout 6 to a divide of 10, 0 deg phase offset, 50/50 duty cycle
          .S1_CLKOUT6_DIVIDE(10),
          .S1_CLKOUT6_PHASE(000_000),
          .S1_CLKOUT6_DUTY(50000),
    
          //***********************************************************************
          // State 2 Parameters - These are for the second reconfiguration state.
          //***********************************************************************
          .S2_CLKFBOUT_MULT(7),
          .S2_CLKFBOUT_PHASE(000_000),
          .S2_CLKFBOUT_FRAC(000),
          .S2_CLKFBOUT_FRAC_EN(0),
    
          .S2_BANDWIDTH("OPTIMIZED"),
          .S2_DIVCLK_DIVIDE(1),
    
          // Set clockout 0 to a divide of 4.750, 0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT0_DIVIDE(7),
          .S2_CLKOUT0_PHASE(000_000),
          .S2_CLKOUT0_DUTY(50000),
          .S2_CLKOUT0_FRAC(000),
          .S2_CLKOUT0_FRAC_EN(0),
    
          // Set clockout 1 to a divide of 1, 45.0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT1_DIVIDE(1),
          .S2_CLKOUT1_PHASE(045_000),
          .S2_CLKOUT1_DUTY(50000),
    
          // Set clock out 0 to a divide of 1, 90.0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT2_DIVIDE(1),
          .S2_CLKOUT2_PHASE(090_000),
          .S2_CLKOUT2_DUTY(90000),
    
          // Set clockout3 to a divide of 1, 135.0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT3_DIVIDE(1),
          .S2_CLKOUT3_PHASE(135_000),
          .S2_CLKOUT3_DUTY(50000),
    
          // Set clockout4 to a divide of 1, 180.0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT4_DIVIDE(1),
          .S2_CLKOUT4_PHASE(180_000),
          .S2_CLKOUT4_DUTY(50000),
    
          // Set clockout5 to a divide of 1, 225.0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT5_DIVIDE(1),
          .S2_CLKOUT5_PHASE(225_000),
          .S2_CLKOUT5_DUTY(50000),
    
          // Set clockout6 to a divide of 1, 270.0 deg phase offset, 50/50 duty cycle
          .S2_CLKOUT6_DIVIDE(1),
          .S2_CLKOUT6_PHASE(270_000),
          .S2_CLKOUT6_DUTY(50000)
       ) mmcme2_drp_inst (
          // Top port connections
          .SADDR(STATE),
          .SEN(sstep_int[0]),
          .RST(RST),
          .SRDY(SRDY),
    
          // Input from IBUFG
          .SCLK(clkin_bufgout),
    
          // Direct connections to the MMCM_ADV
          .DO(dout),
          .DRDY(drdy),
          .LOCKED(LOCKED),
          .DWE(dwe),
          .DEN(den),
          .DADDR(daddr),
          .DI(di),
          .DCLK(dclk),
          .RST_MMCM(rst_mmcm)
       );
    
    		always @ (posedge clkin_bufgout or posedge SSTEP)
    			if (SSTEP) sstep_int <=  8'h80;
    			else  			sstep_int <= {1'b0, sstep_int[7:1]};
    
    endmodule
    Any help is welcome.

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  2. #2
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    Re: How to create an IP core based on a project in ISE?

    FPGA enthusiast!



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  3. #3
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    Re: How to create an IP core based on a project in ISE?

    thanks dpaul ... excuse me how can you create the .ngc file in ISE? I do not find specific information.



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  4. #4
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    Re: How to create an IP core based on a project in ISE?

    Quote Originally Posted by Cesar0182 View Post
    thanks dpaul ... excuse me how can you create the .ngc file in ISE? I do not find specific information.
    You run the design through XST synthesis.



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