Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fixed frequency oscillator in verilogA

Status
Not open for further replies.
Ata_sa16

Ata_sa16

Full Member level 6
Joined
Mar 29, 2016
Messages
343
Helped
59
Reputation
118
Reaction score
58
Trophy points
28
Location
Milky Way Galaxy, 179° 56′ 39.4″
Activity points
2,221
Hi all,

I am new to VerilogA and I have a code which I dont understand. Could you please explain this to me ?
Thank you.

Code: 
// Fixed frequency oscillator
//

module osc1 (out);

output out; voltage out;			// output signal
parameter real freq=1 from (0:inf);		// output frequency
parameter real vl=-1;				// high output voltage
parameter real vh=1;				// low output voltage
parameter real tt=0.01/freq from (0:inf);	// transition time of output
integer n;
real next;

analog begin
    @(initial_step) begin
	next = 0.5/freq + $abstime;
    end
    @(timer(next)) begin
	n = !n;
	next = next + 0.5/freq;
    end
    V(out) <+ transition(n ? vh : vl, 0, tt);
end

endmodule


I dont understand this part

Code: 
analog begin
    @(initial_step) begin
	next = 0.5/freq + $abstime;
    end
    @(timer(next)) begin
	n = !n;
	next = next + 0.5/freq;
    end
    V(out) <+ transition(n ? vh : vl, 0, tt);
end
 

@(initial_step)

--> initialize the variable next to be equal to

next T/2 + the start time (the start time is not necessarily 0 based on if you set the tstart parameter for the transient analysis. T = 1 / freq)

@(timer(next))

-> Once the simulator reaches next (first time this happens is at T/2 + $abstime)

invert/toggle n (from 0 to 1 or vice versa)
increment next = next + T/2, i.e., by another half a clock cycle.

(timer loop will no be entered once clock reaches next + T/2 and redo)

Let V(out) transition to vh if n is 1 or to vl if n is 0 with a risetime of 0 and delay of tt s.
 

jjx said:
@(initial_step)

--> initialize the variable next to be equal to

next T/2 + the start time (the start time is not necessarily 0 based on if you set the tstart parameter for the transient analysis. T = 1 / freq)

@(timer(next))

-> Once the simulator reaches next (first time this happens is at T/2 + $abstime)

invert/toggle n (from 0 to 1 or vice versa)
increment next = next + T/2, i.e., by another half a clock cycle.

(timer loop will no be entered once clock reaches next + T/2 and redo)

Let V(out) transition to vh if n is 1 or to vl if n is 0 with a risetime of 0 and delay of tt s.
Click to expand...

Thank you very much !

- - - Updated - - -

I tried to use this code for oscillator with jitter

Code: 
`include "constants.vams"
`include "disciplines.vams"

module osc (out);
output out; electrical out;
parameter real fc=1.0e+9 from (0:inf);
parameter real Vlo=0, Vhi=1;
parameter real tt=0.01/fc from (0:inf);
parameter real fmJitter=0 from [0:0.1/fc);
parameter real pmJitter=0 from [0:0.1/fc);
integer n, fmSeed, pmSeed;
real next, dT, dt;
analog begin
@(initial_step) begin
fmSeed = 286;
pmSeed = 459;
next = 0.5/fc + $realtime;
end
@(timer(next + dt)) begin
n = !n;
dT = fmJitter*$dist_normal(fmSeed,0,1);
dt = pmJitter*$dist_normal(pmSeed,0,1);
next = next + 0.5/fc + 0.707*dT;
end
V(out) <+ transition(n ? Vhi : Vlo, 0, tt);
end
endmodule


and I did pss simulation in cadence to observe phase noise but I encountered an error

PSS analysis doesn't support behavioral module components with hidden states found in component

I use *ignore_hidden_states* in my code. This fixes the error but this time pss simulation does not converge.
 
Last edited:

ok,

convergence issues are always a bit tricky to deal with.

Possibly:

You could try to soften the transition a bit by introducing rise and fall times.

Also, how do you define dt? Probably initiated to 0, I presume, but maybe set dt to something before using it in timer(next + dt) in your initial_step part.

Further on, even through next is a big number compared to dt (i assume?) but still watch out for the next + delta_time becoming negative numbers.

Also - you have in analoglib a phase-noise generator (I think?) allowing you to generate a sinusoid with a phase noise spectral density mask definition. Maybe it's easier to use if you bump into too many convergence issues.
 
jjx said:
ok,

convergence issues are always a bit tricky to deal with.

Possibly:

You could try to soften the transition a bit by introducing rise and fall times.

Also, how do you define dt? Probably initiated to 0, I presume, but maybe set dt to something before using it in timer(next + dt) in your initial_step part.

Further on, even through next is a big number compared to dt (i assume?) but still watch out for the next + delta_time becoming negative numbers.

Also - you have in analoglib a phase-noise generator (I think?) allowing you to generate a sinusoid with a phase noise spectral density mask definition. Maybe it's easier to use if you bump into too many convergence issues.
Click to expand...

Thank you. I used the vsource in analoglib and you can define noise/frequency points.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top