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  1. #121
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    Re: AXI arvalid signal issue

    Quote Originally Posted by dpaul View Post
    This is your investigation as you have the environment set with the slave instantiated.

    changing ARADDR to 1 also does not work, I suspect the data is not actually written, but we have BVALID asserted and BRESP is ok

    Can you not add-to-wave and investiage the slave internal signals? See if your data is getting latched after the address and write-data handshakes.
    All I can say is that Xilinx AXI based cores might have bugs (they don't perform formal verification of their AXI based cores).

    On another note, if there is an AXI Interconnect b/w the master and slave, then you might want to investigate the interface signals there.
    Before blaming Xilinx IP - be very sure that your cores are functioning correctly.

    This sounds very much like a slave issue. @promach. Telling us that it doesnt work helps no one, and we cannot help you. Unless you post your code, AND your test envirmnent, or a small example exhibiting the problems, there is nothing more we can do.



  2. #122
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    Re: AXI arvalid signal issue

    Unless you post your code, AND your test envirmnent, or a small example exhibiting the problems, there is nothing more we can do.
    See https://gist.github.com/promach/251c...instructions-v

    I have two AXi interfaces. I am only testing the one of the AXi interfaces.

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    `define LOOPBACK 1
     
    module read_instructions(clk, reset,
                i_axi_awready, o_axi_awid, o_axi_awaddr, o_axi_awlen, o_axi_awsize, o_axi_awburst,
                o_axi_awlock, o_axi_awcache, o_axi_awprot, o_axi_awqos, o_axi_awvalid,
                i_axi_wready, o_axi_wdata, o_axi_wstrb, o_axi_wlast, o_axi_wvalid,
                i_axi_bid, i_axi_bresp, i_axi_bvalid, o_axi_bready, 
                i_axi_arready, o_axi_arid, o_axi_araddr, o_axi_arlen, o_axi_arsize, o_axi_arburst,
                o_axi_arlock, o_axi_arcache, o_axi_arprot, o_axi_arqos, o_axi_arvalid,
                i_axi_rid, i_axi_rresp, i_axi_rvalid, i_axi_rdata, i_axi_rlast, o_axi_rready);
     
     
     
     
    `ifdef FORMAL
        // AXI Address width (log wordsize) for DDR
        parameter C_AXI_ADDR_WIDTH = 9; // just for random test, need to change for actual neural network
        parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
        parameter C_SIZE_OF_CACHE = 4; // for storing weights and biases parameters of neural network
    `else
        // AXI Address width (log wordsize) for DDR
        parameter C_AXI_ADDR_WIDTH = 12; // just for random test, need to change for actual neural network
        parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
        parameter C_SIZE_OF_CACHE = 64; // for storing weights and biases parameters of neural network
    `endif
     
    parameter C_AXI_ID_WIDTH    =   1;
     
    localparam NUM_OF_BITS_PER_BYTES = 8;
    localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
     
    // AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. 
    // Support for all other burst types in AXI4 remains at 1 to 16 transfers.
    // for wrapping bursts, the burst length must be 2, 4, 8, or 16
    // a burst must not cross a 4KB address boundary
    // early termination of bursts is not supported
    localparam MAX_BURST_LENGTH = 255; 
     
    localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
    localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
    localparam PROT_BITWIDTH = 3;
    localparam QOS_BITWIDTH = 4;
    localparam CACHE_BITWIDTH = 4;
     
     
    input clk, reset;
     
    // AXI write address channel signals
        input   wire            i_axi_awready; // Slave is ready to accept
        output  wire    [C_AXI_ID_WIDTH-1:0]    o_axi_awid; // Write ID
        output  reg [C_AXI_ADDR_WIDTH-1:0]  o_axi_awaddr;   // Write address
        output  wire    [$clog2(MAX_BURST_LENGTH)-1:0]      o_axi_awlen;    // Write Burst Length
        output  wire    [BURST_SIZE_ENCODING_WIDTH-1:0]     o_axi_awsize;   // Write Burst size
        output  wire    [1:0]       o_axi_awburst;  // Write Burst type
        output  wire    [0:0]       o_axi_awlock;   // Write lock type
        output  wire    [CACHE_BITWIDTH-1:0]        o_axi_awcache;  // Write Cache type
        output  wire    [PROT_BITWIDTH-1:0]     o_axi_awprot;   // Write Protection type
        output  wire    [QOS_BITWIDTH-1:0]      o_axi_awqos;    // Write Quality of Svc
        output  reg         o_axi_awvalid;  // Write address valid
     
    // AXI write data channel signals
        input   wire            i_axi_wready;  // Write data ready
        output  reg [C_AXI_DATA_WIDTH-1:0]  o_axi_wdata;    // Write data
        output  reg [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] o_axi_wstrb;   // Write strobes
        output  reg         o_axi_wlast;    // Last write transaction
        output  reg         o_axi_wvalid;   // Write valid
     
    // AXI write response channel signals
    /* verilator lint_off UNUSED */
        input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid;  // Response ID
    /* verilator lint_on UNUSED */
        input   wire [1:0]      i_axi_bresp;    // Write response
        input   wire            i_axi_bvalid;  // Write reponse valid
        output  wire            o_axi_bready;  // Response ready
     
    // AXI read address channel signals
        input   wire            i_axi_arready;  // Read address ready
        output  wire    [C_AXI_ID_WIDTH-1:0]    o_axi_arid; // Read ID
        output  reg [C_AXI_ADDR_WIDTH-1:0]  o_axi_araddr;   // Read address
        output  wire    [$clog2(MAX_BURST_LENGTH)-1:0]      o_axi_arlen;    // Read Burst Length
        output  wire    [BURST_SIZE_ENCODING_WIDTH-1:0]     o_axi_arsize;   // Read Burst size
        output  wire    [1:0]       o_axi_arburst;  // Read Burst type
        output  wire    [0:0]       o_axi_arlock;   // Read lock type
        output  wire    [CACHE_BITWIDTH-1:0]        o_axi_arcache;  // Read Cache type
        output  wire    [PROT_BITWIDTH-1:0]     o_axi_arprot;   // Read Protection type
        output  wire    [QOS_BITWIDTH-1:0]      o_axi_arqos;    // Read Quality of Svc
        output  reg         o_axi_arvalid;  // Read address valid
     
    /* verilator lint_off UNUSED */
    // AXI read data channel signals
        input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid;     // Response ID
    /* verilator lint_on UNUSED */
        input   wire    [1:0]       i_axi_rresp;   // Read response
        input   wire            i_axi_rvalid;  // Read reponse valid
        input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata;    // Read data
        input   wire            i_axi_rlast;    // Read last
        output  wire            o_axi_rready;  // Read Response ready
     
     
     
     
    always @(posedge clk) 
    begin
        if(reset) o_axi_wstrb <= 0;
     
        // burst alignment mechanism, see [url]https://i.imgur.com/jKbzfFo.png[/url]
        // o_axi_wstrb <= (~0) << (o_axi_awaddr % o_axi_awlen);
        // all the bracket variables are for removing verilator width warnings
     
        else o_axi_wstrb <= ((~0) << (o_axi_awaddr % 
                                      {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
    end
     
    wire write_response_is_ok = i_axi_bvalid && ((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
     
    // need to implement data re-transmission
    wire write_response_is_not_ok = i_axi_bvalid && !((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
     
     
    always @(posedge clk) 
    begin
        if(reset) 
        begin 
            o_axi_wvalid <= 0;
        end
     
        else if(!(o_axi_wvalid && !i_axi_wready))
        begin
            // Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware
            // since this is for testing, WDATA just uses some values up to the total size of the write address space
            // Note: a master must not wait for AWREADY to be asserted before driving WVALID
            o_axi_wvalid <= (o_axi_wlast) ? 0 : 
                            (o_axi_wdata < (o_axi_awsize*o_axi_awlen)); 
        end
    end
     
    wire ddr_write_address_range_is_valid = (o_axi_awaddr < (1 << C_AXI_ADDR_WIDTH));
     
    always @(posedge clk) 
    begin   
        if(reset) o_axi_awvalid <= 0;
     
        // AXI specification: A3.3.1 Dependencies between channel handshake signal
        // the VALID signal of the AXI interface sending information must not be dependent on 
        // the READY signal of the AXI interface receiving that information
        // this is to prevent deadlock 
        // since AXI slave could wait for i_axi_awvalid to be true before setting o_axi_awready true.
        // Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
        // Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
        //       VALID signal needs to be set (initially) independent of READY signal, 
        //       and then only ever adjusted if !(VALID && !READY)
        // Note: the master must not wait for the slave to assert AWREADY before asserting AWVALID
        // Note: (!(o_axi_awvalid && !i_axi_awready)) == (!awvalid || awready) 
        //       == (!awvalid || (awvalid && awready)). 
        //       it means "no transaction in progress or transaction accepted"
        else if(!(o_axi_awvalid && !i_axi_awready))
                o_axi_awvalid <= /*i_axi_awready &&*/ (ddr_write_address_range_is_valid);
    end
     
    wire write_transaction_is_accepted = (o_axi_wvalid) && (i_axi_wready);
    wire address_write_transaction_is_accepted = (o_axi_awvalid) && (i_axi_awready);
     
    always @(posedge clk)
    begin
        if(reset) 
        begin
            o_axi_awaddr <= 0;
            //o_axi_wdata <= 0;
        end
     
        else if(address_write_transaction_is_accepted) 
        begin
            o_axi_awaddr <= o_axi_awaddr + 1;
            //o_axi_wdata <= o_axi_wdata + 1;
        end
    end
     
    always @(posedge clk)
    begin
        if(reset) 
        begin
            //o_axi_awaddr <= 0;
            o_axi_wdata <= 0;
        end
     
        else if(write_transaction_is_accepted) 
        begin
            //o_axi_awaddr <= o_axi_awaddr + 1;
            o_axi_wdata <= o_axi_wdata + 1;
        end
    end
     
    `ifdef LOOPBACK
    wire read_address_contains_loopback_data = 
    (o_axi_awaddr > (o_axi_araddr + {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
    `endif
     
    wire ddr_read_address_range_is_valid = (o_axi_araddr < (1 << C_AXI_ADDR_WIDTH));
     
     
    always @(posedge clk) 
    begin   
        if(reset) o_axi_arvalid <= 0;
     
        // AXI specification: A3.3.1 Dependencies between channel handshake signal
        // the VALID signal of the AXI interface sending information must not be dependent on 
        // the READY signal of the AXI interface receiving that information
        // this is to prevent deadlock 
        // since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
        // Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
        // Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
        //       VALID signal needs to be set (initially) independent of READY signal, 
        //       and then only ever adjusted if !(VALID && !READY)
        // Note: the master must not wait for the slave to assert ARREADY before asserting ARVALID
        // Note: (!(o_axi_arvalid && !i_axi_arready)) == (!arvalid || arready) 
        //       == (!arvalid || (arvalid && arready)). 
        //       it means "no transaction in progress or transaction accepted"
        // Note: o_axi_rready is used for backpressure mechanism
        else if(!(o_axi_arvalid && !i_axi_arready))
            `ifdef LOOPBACK
                o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_read_address_range_is_valid) && 
                                (read_address_contains_loopback_data) && 
                                (o_axi_bready && i_axi_bvalid && write_response_is_ok);
            `else
                o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_read_address_range_is_valid);
            `endif
    end
     
     
    reg [$clog2(MAX_BURST_LENGTH)-1:0] num_of_write_transactions;
     
    always @(posedge clk) 
    begin   
        if(reset) num_of_write_transactions <= 0;
     
        else if(o_axi_wvalid && i_axi_wready)
                num_of_write_transactions <= (o_axi_wlast) ? 0 : num_of_write_transactions + 1;
    end
     
    always @(posedge clk) 
    begin   
        if(reset) o_axi_wlast <= 0;
     
        else o_axi_wlast <= (num_of_write_transactions == (o_axi_awlen - 1));
    end
     
     
    //assign o_axi_wlast = 0;
    assign o_axi_awid = 0;
    assign o_axi_awlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
     
    /* verilator lint_off WIDTH */
    assign o_axi_awsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
    // Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
    /* verilator lint_on WIDTH */
     
    assign o_axi_awburst = INCR_BURST_TYPE;
    assign o_axi_awlock = 0;
    assign o_axi_awcache = 0;
    assign o_axi_awprot = 0;
    assign o_axi_awqos = 0; // no priority or QoS concept
     
     
     
    assign o_axi_arqos = 0; // no priority or QoS concept
    assign o_axi_arburst = INCR_BURST_TYPE;
     
    /* verilator lint_off WIDTH */
    assign o_axi_arsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
    // Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
    /* verilator lint_on WIDTH */
     
    assign o_axi_arlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
    assign o_axi_arprot = 3'b010; // {data access, non-secure access, unprivileged access}
    assign o_axi_arlock = 0; // AXI4 does not support locked transactions. 
    assign o_axi_arcache = 0; // mostly used for HPS (hard processor system) such as ARM hard CPU IP
     
    assign o_axi_arid = 0; // there is one AXI slave which is the DDR memory (A, B, or C) ?
     
    // what situations will render data requester (AXI master) busy to receive read response ??
    // such as AXI interconnect where arbitration will fail to acquire the data transfer priority
    // such as the internal cache storage to store the data from external DDR memory is now full
    // So, let's use a random value that is $anyseq in formal verification
    assign o_axi_rready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (!cache_is_full) `endif; 
     
    // The master can assert BREADY before BVALID is asserted.
    assign o_axi_bready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (i_axi_bvalid) `endif; 
     
    wire address_read_transaction_is_accepted = (o_axi_arvalid) && (i_axi_arready);
     
    always @(posedge clk)
    begin
        if(reset) o_axi_araddr <= 0;
     
        // When ARVALID & ARREADY are both high the next ARADDR can be generated 
        // because the current address for the current transfer is now complete (ARVALID & ARREADY).
        else if(address_read_transaction_is_accepted) 
            o_axi_araddr <= o_axi_araddr + 1; // increments DDR address to read instructions from
    end
     
     
    /* verilator lint_off UNUSED */
    wire arm_write_param_enable;
    wire [C_AXI_DATA_WIDTH-1:0] arm_write_param_data;
     
    wire cache_is_empty;
     
    wire [$clog2(C_SIZE_OF_CACHE)-1:0] cache_address_for_reading;
    assign cache_address_for_reading = 0; // for testing only
    /* verilator lint_on UNUSED */
     
     
    wire valid_read_response_does_not_contain_error_messages = i_axi_rvalid && (i_axi_rresp == 0);
     
    wire cache_is_full; // needed since C_SIZE_OF_CACHE is always smaller than SIZE_OF_DDR_MEMORY
     
     
    // for storing neural network parameters (weights and biases) at destination side, 
    // so this bram acts as intermediate cache (much smaller size than DDR memory) for the neural network
    // no need AXI protocol in order to save logic usage, thus lesser area and power consumption
    cache_controller #(.C_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_SIZE_OF_CACHE(C_SIZE_OF_CACHE)) nn_feature_cache 
    (
        .clk(clk), .reset(reset),
        .i_data(i_axi_rdata), // NN params coming from DDR memory
        .i_data_is_valid
         ((o_axi_rready && valid_read_response_does_not_contain_error_messages)), // DDR data is valid
        .i_addr(cache_address_for_reading),
        .full(cache_is_full), // NN params cache is full
        .o_data(arm_write_param_data), // NN params going to neural network layers
        .o_data_is_valid(arm_write_param_enable), // neural network layers to start another intermediate computations
        .empty(cache_is_empty) // no NN params to feed into the neural network layers
    );
     
    `ifdef FORMAL
     
    localparam SIXTH_ADDRESS_IN_REQUEST = 6;
     
    initial assume(reset);
     
    reg first_clock_had_passed = 0;
     
    always @(posedge clk) first_clock_had_passed <= 1;
     
    always @(posedge clk) 
        if(first_clock_had_passed) 
            cover((o_axi_araddr > SIXTH_ADDRESS_IN_REQUEST) && address_read_transaction_is_accepted &&
                    $past(i_axi_arready) && $past(o_axi_rready) && !o_axi_rready);
     
    `endif
     
    endmodule



  3. #123
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    Re: AXI arvalid signal issue

    You will struggle to find anyone to do your work for you. That is a lot of code to test. Why not specify what the problem is with a clear SMALL usecase example. Or ask more specific questions?
    You dont provide any specific problems, or help us. 120 posts in now.

    Why cant you just debug the slave?



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  4. #124
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    Re: AXI arvalid signal issue

    That is why I never provide code to ask about the wrong AXI waveform until someone asks for the code. And data loopback test is already a SMALL testcase.

    From my personal AXi experience with locating which signals to debug, there is actually not really much a need to check the code if waveform could tells it all, in my case, RDATA returns XXX unknown bits for data loopback case.

    I had already asked very specific question about the simulation waveform. See posts #115 and #116

    As for the slave, I do not have the source code of Xilinx BRAM IP. And I am only provided with its slave AXI interface signals.



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    Re: AXI arvalid signal issue

    Is it true that XILINX AXI slave IP does not support simultaneous two-way data transfer ?

    In other words, for different AWADDR and ARADDR, AW* channel cannot be active when AR* channel is active ?



  6. #126
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    Re: AXI arvalid signal issue

    Is it true that XILINX AXI slave IP does not support simultaneous two-way data transfer ?
    In other words, for different AWADDR and ARADDR, AW* channel cannot be active when AR* channel is active ?
    Should not be. Better you ask this in the Xilinx forums.

    As for your AXI enlightenment and wisdom, I would recommend reading all the AXI related articles in this blog.
    https://zipcpu.com/formal/2019/09/06/axi-story.html
    FPGA enthusiast!


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