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Question Regarding Max Current Per Width

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OrangeHalo

OrangeHalo

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Hey folks,

I am doing some power IC staff. In the design, I am supposed to find the max current density of a transistor to make sure the chip not being on fire. Could you guys help me out? I am using TSMC 180 tech. I could not find the description of the max current density of the MOSFET in tech files.

Best,
OH
 

Normally, every technology provided by the foundry (and definitely - 180nm from TSMC), comes with rules for current densities for electromigration.

These rules are described in electrical deign rule manual.

Also, it comes (at leas, for the advanced technology nodes) with special files describing these rules (ict, itf, etc.).

These current density rule are specified for metals / vias / contacts, but not for MOSFETs.

Once you find these rules, you have to apply them for your current flow simulation in power MOSFETs.
Simulating this is not a trivial task, because regular parasitic extraction + SPICE simulation does not work well, normally, for power FET layouts.
 
I design power products (layout) as mentioned the foundry design rules will provide max current density, take into account tempreture changes and balanced roututing, you may also want to concider using combs.

We use a tool called magwel to simulate the layout, it's quite good but needs CAD support to set it up.

https://www.magwel.com/products/ptmtr/
 

Hi k_90,

Thanks a lot! I think I can try it out if I have the licence.

OrangeHalo
 

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