Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Take different output value from array every clock cycle

Status
Not open for further replies.
M

Mai89

Junior Member level 2
Joined
Jun 5, 2019
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
134
In this code i have input called IP i want to divide it into sub-parts and each part appear in output (SUb_M) every clock cycle, but after simulation output remains at the same value at every clock cycle (which is the first part)
I need SUb_m to be changed at every clcok cycle.



Code: 
process (clk, en)
begin
for i in 0 to addi-1 loop
if(clk='1' and clk'event) then
   if(EN='1') then 

Sub_M <= w(i);  --- w is an array 

end if;[syntax=vhdl][/syntax]
 

I would have thought you would get a multiple driver warning, but we can't see all of the code. Your problem is you are writing this as software. A FOR loop doesn't loop like software, it's a shortcut for typing. Search for "VHDL FOR LOOPS" and you will find many examples of how to use them. To solve your problem you need to make your own counter that increments every EN='1' cycle and use that to reference the array location.
 
  • Like
Reactions: Mai89

    M

    Mai89

    Points: 2
    Helpful Answer Positive Rating
bking, you won't get a multiple driver warning, as the VHDL loop is unrolled and only the last assignment Sub_M <= w(addi-1); gets assigned.

OP what you wrote does this.
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12

process (clk, en)
begin
if(clk='1' and clk'event) then
   if(EN='1') then 
      Sub_M <= w(0);
      Sub_M <= w(1);
      -- ...
      Sub_M <= w(addi-3);
      Sub_M <= w(addi-2);
      Sub_M <= w(addi-1);  -- this is the final assignment to Sub_M so it is the  *only* assignment that maters
   end if;
end if;


To output each w in sequence on each clock cycle you want to do something like this.
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11

process (clk)  -- en was unnecessary as the process is "clocked"
begin
  if rising_edge(clk) then
    if (en='1') then
      Sub_M <= w(idx);
      idx <= idx +1;
    else
      idx <= 0;  -- clear it when not enabled in lieu of any reset in this code.
    end if;
  end if;
end process;
 
  • Like
Reactions: Mai89

    M

    Mai89

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top