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just do a search "impact of scaling down" in google.
**broken link removed**
takes more current to meet peak linearity, peak noise figure and so on.
you can find many papers through google or ieee on this topic.
also i know that 0.13 has many metal layers -8- so even with the digital logic process you can make OK passives, also voltage is low, 1.2V so you need to do folding and get away from cascodes, but the penalty is higher current and power dissipation.
If you sweep bias current for a MOSFET over linearity (IP3) or noise figure (NF), the linearity will have a peak point, while the noise figure will be like a bathtub curve, a parabola like shape with a minimum point.
As RFCMOS scales down you need more current to reach those points, more accurately current density (mA/um) which is current per device size.
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