+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Newbie level 5
    Points: 363, Level: 4

    Join Date
    Jun 2018
    Posts
    10
    Helped
    0 / 0
    Points
    363
    Level
    4

    Design not simulating for different technology node

    Hello Forum,
    I did post synthesis simulation on netlist generated for two different technology nodes(28nm & 40nm) for the same design. The post synthesis netlist simulation worked for 28nm technology node, but it didn't work for 40nm node. The design met timing in both technology nodes. I checked the library setup and everything looks good. I am using the same testbench.

    I'm running out of idea, so I need your wisdom. Thank you very much for your time.

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 9,218, Level: 22

    Join Date
    Apr 2016
    Posts
    1,923
    Helped
    339 / 339
    Points
    9,218
    Level
    22

    Re: Design not simulating for different technology node

    Quote Originally Posted by vyella1 View Post
    Hello Forum,
    I did post synthesis simulation on netlist generated for two different technology nodes(28nm & 40nm) for the same design. The post synthesis netlist simulation worked for 28nm technology node, but it didn't work for 40nm node. The design met timing in both technology nodes. I checked the library setup and everything looks good. I am using the same testbench.

    I'm running out of idea, so I need your wisdom. Thank you very much for your time.
    I need to know a lot more about the setup. My first comment is that if you just take the testbench as is, it is unlikely to work for both netlists. I assume the 28nm version is much faster, and that your clock period has to be adjusted accordingly for both cases. If you are doing delay annotated simulation, you naturally need unique SDF files for each netlist.
    Really, I am not Sam.



    •   AltAdvertisement

        
       

  3. #3
    Newbie level 5
    Points: 363, Level: 4

    Join Date
    Jun 2018
    Posts
    10
    Helped
    0 / 0
    Points
    363
    Level
    4

    Re: Design not simulating for different technology node

    Hello ThisIsNotSam,
    I synthesized the design at 600Mhz for 28nm technology and 400Mhz for 40nm technology. My testbench runs at 100Mhz. I am not using the SDF files. Instead I am using unit delays specified in the standard cells verilog file. The goal is to generate saif files for respective netlists.

    I fixed the issue. The issue was in 40nm standard cells verilog file, for some of the sequential cells the unit delays are not specified and for some cells the macro to turn on the unit delays is not working. I am surprised to see such bugs in the standard cell libraries.



    •   AltAdvertisement

        
       

  4. #4
    Super Moderator
    Points: 32,398, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,489
    Helped
    1758 / 1758
    Points
    32,398
    Level
    43

    Re: Design not simulating for different technology node

    Quote Originally Posted by vyella1 View Post
    I fixed the issue. The issue was in 40nm standard cells verilog file, for some of the sequential cells the unit delays are not specified and for some cells the macro to turn on the unit delays is not working. I am surprised to see such bugs in the standard cell libraries.
    It's highly dependent on the quality of the standard cell library engineer writing the code.

    It's not an ASIC library but Xllinx has had issues with having junior engineers writing their primitive models in the past. I've seen misbehavior for ddr registers that actually had race conditions in the model, which were "fixed" by a bunch of #delays on the clock to delay the clock in multiple places. A very bad model that did not emulated the actual device. I had to pull the primitive from the old ASIC style library and compile it (did this for at least 5 years after I found the problem and reported it). Had to do this with a couple of other primitives as this junior engineer messed up a bunch of the primitives.

    Eventually they must have been a layoff that got rid of that person (or they got promoted to management ) and an ASIC library engineer took over and tossed out all the code done by the previous engineer. Interestingly the old version of the ddr or something oddly similar was in the next release.



--[[ ]]--