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high speed latch problem

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yefj

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Hello, i am trying to implement this high speed CML latch,shown bellow, where the right side stores the data each clock and the left side senses it.
From the input and out put shown bellow i see that the output just copies the CLK with small amplitude near the VDD value of 1.8V.
What are the design considations needs to be taken in order to make it Latch correctly?
Thanks.

latch.JPG
schematics.JPG
time_input.JPG
input_output.JPG
 

i don't know, but i suggest you meet set up and hold times
your device may require the D set longer before the clock arrives
and it may need the D to be held some time after the clock edge
 

There is no plot of CLK_minus, what is it doing?

CLK is not ppropriate as a CML input, you cut off the input
pair hard every time you put it to zero. If CLK_minus does
the same then you may have an interval where both
sides are cut off. You need to ensure the CLK-phase
"handoff" is correct or your "relay race" is ruined.

For realism's sake you ought to be driving the D-pair
and CLK-pair with CML level signals. You may want
to see what those are supposed to be (designs vary,
but output swing looks low and you may need to
change tail/load resistor ratio, ensure that FETs are
sized to be switches and not high value resistors when
"on", etc. A swing of about VT(N) is probably "roughly
right" for a "regular" / "high" VT device choice. A zero-
or low-VT transistor may have trouble getting input
and output levels to coincide neatly (Vds(off) = Vgs(on)).
 

Hello for some reason the resistor drops the level of the low value of output signal as seen bellow,Why is that?
Also as you can see we have here a full FLIP FLOP rising edge behavior ,also its supposed to be only a LATCH.
Is it a behavior of flip flop or of a latch?
Thanks.

res.JPG
 

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