yefj
Advanced Member level 4
Hello, i am trying to implement this high speed CML latch,shown bellow, where the right side stores the data each clock and the left side senses it.
From the input and out put shown bellow i see that the output just copies the CLK with small amplitude near the VDD value of 1.8V.
What are the design considations needs to be taken in order to make it Latch correctly?
Thanks.
From the input and out put shown bellow i see that the output just copies the CLK with small amplitude near the VDD value of 1.8V.
What are the design considations needs to be taken in order to make it Latch correctly?
Thanks.