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    Array storage in an FPGA, How is it handled?

    I have a Deo nano SOC. When I create an array using VHDL on the FPGA part, where is the array data stored?

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    Re: Array storage in an FPGA, How is it handled?

    By default assume it's stored in a lut flip flop.

    However if your FPGA has block ram the tool may fit the array to ram if the way you implement and use it is compatible with that. See the output of your tool - it will print a message telling you when it infers a block ram.



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    Re: Array storage in an FPGA, How is it handled?

    Quote Originally Posted by asdf44 View Post
    By default assume it's stored in a lut flip flop.

    However if your FPGA has block ram the tool may fit the array to ram if the way you implement and use it is compatible with that. See the output of your tool - it will print a message telling you when it infers a block ram.
    I am using Quartus Prime. My demo board has a CPU, RAM and an FPGA. Where do I look to find this info? Also, I did not start my code from scratch. It is built on an existing code.



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    Re: Array storage in an FPGA, How is it handled?

    Quote Originally Posted by FPGAwarrior View Post
    I am using Quartus Prime. My demo board has a CPU, RAM and an FPGA. Where do I look to find this info? Also, I did not start my code from scratch. It is built on an existing code.
    Synthesis report will show how it implemented an array in the code.

    Using existing code doesn't guarantee anything, even proper functionality. Unless a piece of code has a regression suite that I can re-run and check for coverage, I always assume that existing code I have to use doesn't necessarily function correctly.

    The coding of an array to be implemented in RAM is usually called out in the vendors synthesis documentation. This usually involves registering the correct port, not having resets on the array, and having the read and write signals properly implemented.



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    Re: Array storage in an FPGA, How is it handled?

    Quote Originally Posted by ads-ee View Post
    Synthesis report will show how it implemented an array in the code.

    Using existing code doesn't guarantee anything, even proper functionality. Unless a piece of code has a regression suite that I can re-run and check for coverage, I always assume that existing code I have to use doesn't necessarily function correctly.

    The coding of an array to be implemented in RAM is usually called out in the vendors synthesis documentation. This usually involves registering the correct port, not having resets on the array, and having the read and write signals properly implemented.
    Thanks. I saw in a report what appears to be an auto RAM system that utilizes a few hundred KB. Apparently, it does use part of the CPU RAM.



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    Re: Array storage in an FPGA, How is it handled?

    Quote Originally Posted by FPGAwarrior View Post
    Thanks. I saw in a report what appears to be an auto RAM system that utilizes a few hundred KB. Apparently, it does use part of the CPU RAM.
    If you say so...

    Lack of design files, block diagrams, synthesis reports, or anything of value to determine if that is your array or not. It might by your array or it might just be part of the CPU (assuming you have an embedded CPU inside the FPGA).



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