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Fractional N Synthesizer - Dual or Multi-Modulus Divider

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doctorworm

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Hi folks,

I'm having trouble finding equations or literature on how to design a suitable frequency divider.

Ignoring the sigma-delta stuff (for now), I want to know how to "hit" every channel in a fractional-N PLL synth. Let's say I know the frequency step (channel spacing), reference (comparison) frequency and the VCO output range.

I have the choice of a dual-modulus divider or a multi-modulus divider. Apparently the dual-modulus divider might not give me all the channels in the range but I don't know how true this is!

The reference frequency has to be an integer division of whatever the Xtal frequency is and I guess the accumulator size, n, means that the total number of cycles has to be 2^n. These limitations don't make life easier.

So... how can I choose which type of divider will achieve this and also how can I work out which division ratios (N/N+1 etc) will give me every single channel in the output range?

Apologies if I've broken any rules - this is my first (or second) post so please go easy on me!

Cheers!
 

Hi,

I can't follow this vague description.

Please post a picture of your topology and give an example with values.

Maybe you are looking for a mathematical solution.
Then often prime factorization is used.


Klaus
 

Hi Klaus,

Apologies if my description was vague. You're right about finding a general mathematical solution. I've attached a very crude PLL diagram with some arbitrary numbers as an example so please forgive any unrealistic values.

Let's say I want to design a synth whose output, f_VCO, is 690 - 960 MHz with a 100 kHz channel spacing, f_step. If my reference frequency, f_ref is 10 MHz, then I need a divider which can divide f_VCO by 69 and 96 and all the steps between. So, for a 100 KHz step, this means I need to divide f_VCO in a way that ensures I can reach all 2710 channels in the 690 - 960 MHz range.

Since it's fractional-N, I can use a dual-modulus or multi-modulus divider but I don't know which type of divider would allow me to select all the output frequencies. Once I know what's possible, I'll then need to find out how to program the divider in order to select those frequencies.

I've seen a few descriptions in some theses and papers but no generalised solution.

PLL.png
 

You can use either. The dual modulus divider will introduce more jitter (due to quantization) than a multi-modulus divider in general. But you need to make a MATLAB model for it to see its impact and if it affects your performance too much.
Refer to Razavi's RF Microelectronics (fractional-N synthesizer chapter).
 

Thanks for your help. I've got the Razavi book stashed away somewhere so will dig it out and take a look.

Also, the jitter/phase noise/spurs issue is something I'll worry about once I've found a generalised solution.

Is there a test I can do to check whether or not the dual modulus divider is sufficient?

From what I've read, in a fractional-N PLL, the channel spacing, f_step, is dictated by f_step = f_ref / (2^K), where K = accumulator size in bits. Now, if f_ref is to be an integer division of the crystal frequency, f_xtal, and (2^K) can be 1, 2, 4, 8 … 32 … 64 ... etc., then for a channel spacing of 100 kHz and f_ref of 10 MHz, K = 13.29. Rounding this to 13 or 14 gives me a channel spacing of 1.22 kHz or 610.4 Hz, respectively. To get the exact 1 kHz frequency step, I'd need to divide the crystal by a non-integer value.

This is before I get to the fun part of finding N/N+1 division ratios which are guaranteed to land exactly on every required frequency point.

(Apologies if this is all wrong - I'm an RF guy by trade and have not had much experience with the digital side of things!)
 

As long as your loop filter has long enough time constant you can switch modulus 'on the fly' to produce intermediate division ratios. You don't have to select the exact division ratio for each frequency, you 'jump' each side of the ratio you need and let the loop filter find the middle ground.

Brian.
 

Hi All,

Please ignore my previous reply - I got myself in a pickle and couldn't make up my mind which frequency step to use.

What I need to know more than anything is, what circuits can I use to achieve the integer division? If my reference, f_ref is 10 MHz and my VCO output range is 690 - 960 MHz, I need a programmable divider, which can divider by 69 and 96 with all integer steps in between.

The fractional steps can of course be achieved by toggling between the two values of N and N+1. As betwixt said, this is averaged by the loop filter.

I just don't know how to make a divider whose value of N can be programmed. Any ideas or even better, some links to a publication or two?

Cheers!
 

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