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    Gain and Phase margin problem

    Hello,
    I am designing the two stage folded cascode opamp. For the single stage of folded cascode i got sufficient phase margin of 64 degree. But when i added the second stage, the phase margin increases to 150 degree. is it correct to have higher phase margin? In order to reduce the phase margin for the required level what should i do? Since i am the beginner of designer of opamp design i don't know how to reduce this.kindly help me.btw the opamp is miller compensated also.
    Thanks in advance

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  2. #2
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    Re: Gain and Phase margin problem

    What kind of 2nd stage do you have? Could you show more details (bode diagram, schematic)? 150° means stable operation, however it is suspicious value. Probably you did something not usual with the devices or the testbench.
    "Try SCE to AUX." /John Aaron/



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    Re: Gain and Phase margin problem

    Thanks for the reply frankrose. The opamp i am using is folded cascode for the first followed by common source as the second stage. Please find the below attached schematic. I am using the load cap as 0.1pF and Compensation cap as 500fF

    1. Two stage opamp bodeplot
    Click image for larger version. 

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    2. Schematic
    Click image for larger version. 

Name:	2stagebodeplot.png 
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Size:	114.1 KB 
ID:	157468

    Waiting for your reply. Thank you



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  4. #4
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    Re: Gain and Phase margin problem

    From what I see, you've got no phase margin - 0deg or even negative, not quite visible from the plot.
    Two comments. You have a fully differential amplifier but i don't see you using a common mode feedback circuit. So, most probably your amplifier is completely off. Can you check what is the DC voltage at the outputs of the first stage and at the outputs of the second stage?

    You are not simulating the loop gain correctly. To simulate it, you have to put the amplifier in a DC closed loop and break the loop in AC. If you are using cadence, you could simply use the iprobe for that. The way you are doing it can not guarantee proper DC bias of your circuit.


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    Re: Gain and Phase margin problem

    I don't want to repeat last comment, all of it is true, you have basic problems with your circuit. Never use DC sources for example to bias current generators, cascodes are ok, but I am almost sure your operating point is unstable even without any feedback AC signal. And please, this drawing you made is almost unvisible with the pell-mell wires. Make your life easier with straight continuous lines.
    About how to simulate full differential opamp here is tutorial: https://www.lumerink.com/courses/ece...l%20Opamps.pdf
    From page 31 it shows how to simulate. But first I recommend you to go back to basics, simplier circuits, fully differential circuits are advanced design.
    "Try SCE to AUX." /John Aaron/


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  6. #6
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    Re: Gain and Phase margin problem

    Thanks for the answer friends. Now I added CMFB to my circuit. But still i am having a problem on Phase margin. The phase degree spectrum doesnt reach -180 rather it suddenly increase. Can you people tell me why is that happening and why am not able to reach the -180 degree. Is it because of the zeroes which i am having in the circuit?? Can you people suggest me the solution ?



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  7. #7
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    Re: Gain and Phase margin problem

    Added to that i already done the stability analysis in cadence by breaking the loop and inserting the iprobe as well. The command window is showing that the loop is unconditionally stable and it is not showing any gain and phase margin values



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    Re: Gain and Phase margin problem

    It will be very helpful if you show your latest schematic, together with the CMFB, the way you break the loop and the plots of your results. Also, if you can back-annotate the DC operating point on the schematic, it will help too. Otherwise you want us to comment on something we don't actually see.
    Last edited by sutapanaki; 29th January 2020 at 19:31.



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