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  1. #1
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    [ Describing PG Pins at RTL Level UPF ]

    Hi,
    I am trying to read in UPF at RTL level.

    For the all standard Cells, Memories, Analog Macros - Power config file is used to add search path and db file name.

    I have the below two observations -
    1- After adding power config file, I have removed the corresponding RTL files of standard Cells, Memories, Analog Macros from file list.
    After giving it a run, I am getting errors that Memory Cells/Standard Cells/Analog Macros designs are not found in the compiled Database

    2- If I add the Verilog models of standard cells/Memories/Analog Macros,
    I am getting errors - that VDD/VSS pins are not found as defined in the UPF.

    Can you please tell me the correct way of reading the
    1. Using the same UPF at RTL level and Gate level
    2. How to specify the power information of Standard Cells

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  2. #2
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    Re: [ Describing PG Pins at RTL Level UPF ]

    Quote Originally Posted by whizkid123 View Post
    Hi,
    I am trying to read in UPF at RTL level.

    For the all standard Cells, Memories, Analog Macros - Power config file is used to add search path and db file name.

    I have the below two observations -
    1- After adding power config file, I have removed the corresponding RTL files of standard Cells, Memories, Analog Macros from file list.
    After giving it a run, I am getting errors that Memory Cells/Standard Cells/Analog Macros designs are not found in the compiled Database

    2- If I add the Verilog models of standard cells/Memories/Analog Macros,
    I am getting errors - that VDD/VSS pins are not found as defined in the UPF.

    Can you please tell me the correct way of reading the
    1. Using the same UPF at RTL level and Gate level
    2. How to specify the power information of Standard Cells
    This is so confusing. What tool are you using, to begin with? What step of the flow are you doing? I can't think of any tool that takes RTL and UPF files.
    Really, I am not Sam.



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