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BJT amplifier design

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King_Ruzin

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Hello everyone,
as a part of a course in analog circuits, I need to design a BJT amplifer with the following parameters:
Voltage gain = 51[dB]
Rin = 55[ohm]
Rout = 50[kohm]
Band width: [10kHz,1MHz]
DC suppliers allowed: +/- 5V
The purpose is to as less stages as possible.
I thought about using two stages : of CB and CE or 2 stages of CB.
the problem is when I tried to obtain bias point, I didnt manage to keep the circuit working propperly while maintaning the requested resistancies and gain.
I would appreciate any kind of help!
thanks guys.
 

51dB (voltage) gain is A=355
A=gm*Rout
assume best case Rout=Rload
Then gm must be 355/50K or 7mA/V

If you can find a transistor with this kind of gm and decent Early voltage then a single CE stage could do it. If Early voltage is a problem then cascode it (CB over CE)
Of course input impedance match will cost some base current so you will need a better gm than 7mA/V at the transistor terminals.

If the bandwidth is meant to indicate a bandpass response (not just fmin must be lower and fmax higher type spec, but fmin=10kHz +/-x%, fmax=1MHz +/-y%) then things are more complicated.

Many missing constraints such as input amplitude range, supply set, whether input and output are DC-blocked, whether the application is analog (dB20, voltage gain) or RF (db10, power gain) in the spec - although given the frequency range I'd assume it's analog, you know what they say about "ASSUME".

First order of business I'd say is to determine whether you can find a transistor with VA/Ic @ Ic=Vsupply/50K >50Kohms (your Rout bogey) and a fT greater than 350MHz (your DC gain * BW specs). Bumped out by what you discover about circuit passive loading and sensitivities (like, your "50K" load cannot be purely resistive, once you attach test equipment or the next element of the signal chain, and your actives / passives / PCB have their baggage as well).

If you can't find "magic in a 3-pin can" then you have to look at topology. 51dB single stage voltage gain is a no-go in many integrated technologies even at DC. Discretes, I don't-really have a sense of what's available if you look hard and spend high enough.

But I bet you were looking for more of a ready solution than additional stuff to consider.


Hello everyone, as a part of a course in analog circuits, I need to design a BJT amplifer with the following parameters:
Voltage gain = 51[dB]
Rin = 55[ohm]
Rout = 50[kohm]
Band width: [10kHz,1MHz]
DC suppliers allowed: +/- 5V
The purpose is to as less stages as possible.
I thought about using two stages : of CB and CE or 2 stages of CB.
the problem is when I tried to obtain bias point, I didnt manage to keep the circuit working propperly while --maintaning the requested resistancies and gain.
I would appreciate any kind of help!
thanks guys.
 
when I tried to obtain bias point, I didnt manage to keep the circuit working propperly while maintaning the requested resistancies and gain.

Common base mode is suitable. It's tricky to adjust bias voltage and current, in order to find a good operating point.

Simple simulation using your specs of Rin, Rout.
Signal is applied at emitter leg. Signal amplitude affects bias, which changes transistor conductivity.

common base amp NPN signal 100mV supply 5VDC.png

This is one stage. To change gain, change bias resistance and voltage. More gain results in less linear response. You may need additional stages if you want 51dB gain.
 
Hi,

are we doing home work for students now ... ?
Yes, and there is an almost identical parallel thread ...with modified values.

@OP:
Show what you have done so far. Your hand made schematic, calculations, ideas...
Tell us what does work and what does not work as expected. Then tell us where exactly you need help.

Klaus
 
Yes, and there is an almost identical parallel thread ...with modified values.
Apparently from the same course, but a considerably different problem.

I presume that the solution can be elaborated based on the course material, which we unfortunately don't know. Thus the questions raised by KlausST should be answered.
Show what you have done so far. Your hand made schematic, calculations, ideas...
Tell us what does work and what does not work as expected.

General hints and comments can be nevertheless helpful.

As far as I see, the specification can be achieved with a single CB stage and an active (current source) load. A load resistor doesn't work for the restricted power supply range.
 
Hello again,
Yes i'm a student for electrical engineering, and teking a course in analog circuits. Unfortunately, design isn't a part of the course at all, only analysis. So i'm a bit clueless because design is quite new to me.
I need to design an amplifier with the specs mentioned above.
I may use as many stages as needed, but the lesser the better.
I tried to use a CB input stage to obtain low Rin and high gain, and a CB output stage in order to get high Rout - by placing a high value resistor, paralleled to the second collector.
The problem was maintaining operation point: because the two stages share the same bias current, the big resistor at the output causing a big voltage drop, taking the second CB into cutoff.
maybe I should use a current mirror between the two stages, or any other stage in order to settle bias point, but i couldnt really figure this out.
I would appreciate any kind of help!
thanks again
 

Moreover,
V Early is infinite, current gain=100 for all transistors.
 
Last edited:

A PsPice schematic of the circuit is attached
 

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I don't think that the problem specification is implemented appropriately. The 50k resistor is useless, the collector current flows almost completely through RL.

Where is the load resistor specified?
 

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