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    FPGA Re-Verification after minimal initial verification with Microsemi IGLOO2

    Hello,

    My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, so that I don't have to verify the whole physical device (Microsemi IGLOO2 FPGA) again.

    There is an already existing tool from OneSpin to make equivalency checking, and there is the option of Libero to create a block flow to make changes to certain blocks but I want to explore other options to see the changes that are done, for example with a tool that compares the 2 netlists or even using word to copy paste and compare the netlists before and after small change, but I don't know where to look into.

    Any help would be much appreciated.

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    Re: FPGA Re-Verification after minimal initial verification with Microsemi IGLOO2

    Are you talking about LEC?

    Here is a list of widely used LEC tools - https://en.wikipedia.org/wiki/Formal...lence_checking and they are expensive.

    I have never compared netlists. Two netlists can be physically different although they can be logically same.

    Perhaps the cheapest and easiest can be netlist comparison.
    You try the Compare plugin for Notepad++ or the tool named Meld for any file comparison.
    FPGA enthusiast!



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    Re: FPGA Re-Verification after minimal initial verification with Microsemi IGLOO2

    Quote Originally Posted by canseyman View Post
    Hello,

    My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, so that I don't have to verify the whole physical device (Microsemi IGLOO2 FPGA) again.

    There is an already existing tool from OneSpin to make equivalency checking, and there is the option of Libero to create a block flow to make changes to certain blocks but I want to explore other options to see the changes that are done, for example with a tool that compares the 2 netlists or even using word to copy paste and compare the netlists before and after small change, but I don't know where to look into.

    Any help would be much appreciated.
    Microsemi tools are not very good at giving consistent results from run to run. Synplify has a habit of making a minor (1 line) change affect multiple unrelated blocks during synthesis. This behavior also appears to be somewhat inconsistent too (changing a constant (version number) in the code resulting in 1000s of differences in one build and 10-20 changes in another). Libero P&R is random number based and will result in different results unless the tools are told to keep previous P&R results, but this is dependent on the synthesis (Synplify) outputting the same edif with minor changes related to the VHDL code change.

    If you want to explore such things you would be better off using either Vivado or Intel tools, In my experience their results are much more consistent between synthesis runs. You can also partition designs in both tools to avoid any changes to synthesis or P&R results for any number of blocks.



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