canseyman
Newbie level 1
Hello,
My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, so that I don't have to verify the whole physical device (Microsemi IGLOO2 FPGA) again.
There is an already existing tool from OneSpin to make equivalency checking, and there is the option of Libero to create a block flow to make changes to certain blocks but I want to explore other options to see the changes that are done, for example with a tool that compares the 2 netlists or even using word to copy paste and compare the netlists before and after small change, but I don't know where to look into.
Any help would be much appreciated.
My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, so that I don't have to verify the whole physical device (Microsemi IGLOO2 FPGA) again.
There is an already existing tool from OneSpin to make equivalency checking, and there is the option of Libero to create a block flow to make changes to certain blocks but I want to explore other options to see the changes that are done, for example with a tool that compares the 2 netlists or even using word to copy paste and compare the netlists before and after small change, but I don't know where to look into.
Any help would be much appreciated.