Hey all,

I am using Verdi for simulation of RTL. We have lot of assertions in design and I would like to know if an assertion is fired in a simulation or not. There is a assertion debug mode which should list out all the assertions, however, I am not seeing any information if it is passing, failing, checked, or not at all fired. Is there some kind of simulation switch or build switch that we need to pass for Verdi to populate this information?

Thanks,
Abhishek