Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verdi: Assertion debug mode question

Status
Not open for further replies.
S

swabhi812

Member level 2
Joined
May 18, 2018
Messages
45
Helped
4
Reputation
8
Reaction score
4
Trophy points
8
Activity points
349
Hey all,

I am using Verdi for simulation of RTL. We have lot of assertions in design and I would like to know if an assertion is fired in a simulation or not. There is a assertion debug mode which should list out all the assertions, however, I am not seeing any information if it is passing, failing, checked, or not at all fired. Is there some kind of simulation switch or build switch that we need to pass for Verdi to populate this information?

Thanks,
Abhishek
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top