Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Understanding LVS results (hierarchical)

Status
Not open for further replies.
A

aditya1579

Member level 2
Joined
Jan 2, 2013
Messages
47
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,624
Hi,

For the error "incorrect ports" in Calibre LVS hierarchical run, why do some ports appear at the top level and others at the IP level ?

What is the basis for them to appear at two levels like this ?

Thanks,
Aditya
 

There's ports all the way down, and hierarchical means
you are checking at levels below the top so you will see
the ports of lower level blocks checked as the local
network equivalence checks run.

I like to do bottom up LVS, the cells as I create them,
so the top level holds fewer mysteries when I get to that.
 

The ports on the layout are defined by text labels "attached" to port/pin text layers.

Normally, the ports are defined at the top level only.

There is a command in Calibre (involving "TEXT DEPTH" statement), that tells how many levels of hierarchy down should be used to find the ports (text labels).
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top