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  1. #1
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    PLL gain and phase margin

    Hello guys,
    I have a PLL design in VerilogA, and I did an 'ams' simulation in cadence that shows that the PLL reaches locking state within 4us]:
    Click image for larger version. 

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    Click image for larger version. 

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    how do I plot the Phase margin and Gain of PLL? i'm trying to do an ac simulation but got confused what to put at the inputs and what signals should I picked to draw the plot.
    when I tried to pick vout/fdiv or vout/fref I got a constant frequency. I couldn't explain the result.

    I have 30Mhz reference clock with N=64 dividing ratio, and locking frequency: 1.9Ghz.

    these are the options that I see in the ADE simulation analysis:

    Click image for larger version. 

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    thanks,
    firas

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  2. #2
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    Re: PLL gain and phase margin

    I guess some more information is needed ... do you break the loop when you do the tests and have you designed the phase detector and charge pump such that they are linearized around the stable operating point?



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    Re: PLL gain and phase margin

    Hi,
    how do I check if they are linearized around a stable operating point? and why reaching a locking state is not equivalent to reaching this point? can you please what does this operation point mean in terms of PLL component output signals?
    and no I don't break the loop, I'm trying first to calculate the closed loop gain, but also open loop is on the list.
    my problem is that I don't know how to technically apply this in Cadence (on transistor level amplifiers for example I know how to do it, there are alot Youtube videos that explain how to calculate Phase and Gain Margin, but since this simulation involves VerilogA 'ams simulation' , it is something new for me ).



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    Re: PLL gain and phase margin

    The PLL is a strong non-linear device.
    It can be seen as a linearized circuit under locked-conditions only - and only under these conditiones you can determin the phase/gain margins.
    However, I am afraid this will be rather complicated for the real circuit.....
    My recommendation: It is rather easy to make a linear MODEL for the locked PLL for performing measurements under open-loop conditions.



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    Re: PLL gain and phase margin

    If you are able to use MatLab , you can replace PLL blocks with their mathematicaly linear models.Otherwise Nonlinear elements won't give you any insight.



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    Re: PLL gain and phase margin

    There are many other programs (other than MATLAB) which can perform such analyses - like allSpice-based packages or VISSIM (just block-oriented).
    I have used the VISSIM simulator with great success for simulating the lock-in process in the time domain.



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    Re: PLL gain and phase margin

    With the PFD in there, you cannot do it. Period.

    What I used to do was create a linear model for the components.

    PFD ==> VCVS with a gain of 1. The positive input is the refclock input and the negative input is the feedback clock.

    Charge pump ==> A current source of value Icp/2pi

    Loop filter ==> this is straight forward and is just RC components.

    VCO ==> integrator. I used to realize this using an ideal current source and a capacitor. The current source/cap value must be equal to the KVCO of the VC0. Make sure to use the correct units (Not Hz/V but rads/s-V).

    Feedback divider ==> another VCVS of a gain 1/N.

    Hope this helps.



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