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  1. #1
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    Does Opentimer tool for STA support VHDL netlist

    Hi,

    Does anyone know if Opentimer tools for STA read VHDL netlist as well?

    Regards,
    Arvind Gupta

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    Re: Does Opentimer tool for STA support VHDL netlist

    Did you read the paper for this tool?

    In the abstract it clearly mentions - "OpenTimer works on industry
    formats (e.g., .v, .spef, .lib, .sdc) and is designed to be parallel and
    portable. " I don't find VHDL.

    Moreover it comes from an American University, a country where Verilog is the dominant RTL language.

    It is better to ask the author for details as I don't think this tool has industrial acceptance yet.
    FPGA enthusiast!



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  3. #3
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    Re: Does Opentimer tool for STA support VHDL netlist

    even if it doesn't, converting a netlist from vhdl to verilog is rather trivial. Both DC and genus can do it for you.
    Really, I am not Sam.



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